wired WRPC UART to zynq peripheral instead of uartlite cause input problems (26a516e4) · Commits · Projects / FPGA and ARM SoC FMC Carrier FASEC

Commit 26a516e4 authored 8 years ago by

Pieter Van Trappen

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wired WRPC UART to zynq peripheral instead of uartlite cause input problems

parent 98cb4228

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FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v 0 additions, 288 deletions

.../ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/synth/system_design_auto_pc_0.v 0 additions, 290 deletions

...p/system_design_auto_pc_0/synth/system_design_auto_pc_0.v
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml 92 additions, 1093 deletions

...gn/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_ooc.xdc 0 additions, 57 deletions

...p/system_design_auto_pc_0/system_design_auto_pc_0_ooc.xdc
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v 0 additions, 348 deletions

.../ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/synth/system_design_auto_pc_1.v 0 additions, 350 deletions

...p/system_design_auto_pc_1/synth/system_design_auto_pc_1.v
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml 92 additions, 1093 deletions

...gn/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_ooc.xdc 0 additions, 57 deletions

...p/system_design_auto_pc_1/system_design_auto_pc_1_ooc.xdc
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci 4 additions, 4 deletions

...sing_system7_0_0/system_design_processing_system7_0_0.xci
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xml 11 additions, 25 deletions

...sing_system7_0_0/system_design_processing_system7_0_0.xml
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v2_9/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd 2 additions, 2 deletions

...c_hwtest_v2_9/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v 0 additions, 883 deletions

...2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v 0 additions, 606 deletions

..._v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v 0 additions, 840 deletions

...ilog/axi_protocol_converter_v2_1_axi_protocol_converter.v
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v 0 additions, 233 deletions

..._1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v 0 additions, 557 deletions

...verter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v 0 additions, 108 deletions

.../hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v 0 additions, 109 deletions

.../hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v 0 additions, 187 deletions

...1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v 0 additions, 147 deletions

.../verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v

with 201 additions and 7277 deletions

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