submodule cores updated for fasec_hwtest v3.2.2, outputs generated
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- .Xil/Vivado-3878-lapte24154/coregen/clock_temp/clock_temp.xci 44 additions, 0 deletions.../Vivado-3878-lapte24154/coregen/clock_temp/clock_temp.xci
- .Xil/Vivado-3878-lapte24154/coregen/clock_temp/clock_temp.xml 91 additions, 0 deletions.../Vivado-3878-lapte24154/coregen/clock_temp/clock_temp.xml
- .Xil/Vivado-3878-lapte24154/coregen/interrupt_temp/interrupt_temp.xci 37 additions, 0 deletions...3878-lapte24154/coregen/interrupt_temp/interrupt_temp.xci
- .Xil/Vivado-3878-lapte24154/coregen/interrupt_temp/interrupt_temp.xml 52 additions, 0 deletions...3878-lapte24154/coregen/interrupt_temp/interrupt_temp.xml
- .Xil/Vivado-3878-lapte24154/coregen/reset_temp/reset_temp.xci 38 additions, 0 deletions.../Vivado-3878-lapte24154/coregen/reset_temp/reset_temp.xci
- .Xil/Vivado-3878-lapte24154/coregen/reset_temp/reset_temp.xml 71 additions, 0 deletions.../Vivado-3878-lapte24154/coregen/reset_temp/reset_temp.xml
- FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd 1 addition, 1 deletion...type.ip_user_files/bd/system_design/hdl/system_design.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd 2 additions, 2 deletions...n_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd 0 additions, 0 deletions...st_v3_2_2/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd 19 additions, 14 deletions...st_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd 0 additions, 0 deletions...hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd 0 additions, 0 deletions...t_v3_2_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd 0 additions, 0 deletions..._v3_2_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd 0 additions, 0 deletions...v3_2_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd 0 additions, 0 deletions...2_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd 0 additions, 0 deletions..._v3_2_2/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd 0 additions, 0 deletions..._2_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/main_pkg.vhd 0 additions, 0 deletions...fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/main_pkg.vhd
- FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt 1 addition, 1 deletion...user_files/sim_scripts/system_design/activehdl/README.txt
- FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do 10 additions, 10 deletions...user_files/sim_scripts/system_design/activehdl/compile.do
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