.../Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xci

.../Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xml

.gitmodules

...type.ip_user_files/bd/system_design/hdl/system_design.vhd

...2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd

...2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd

...c_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v

...wtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl

...r_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd

..._v3_2_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd

..._v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd

...v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd

..._v3_2_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd

...2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd

...0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd

...v3_2_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd

..._2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd

...b_i2c_master_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd

...n.ch/axi_wb_i2c_master_v3_2_0/modules/axis_to_i2c_wbs.vhd

.../axi_wb_i2c_master_v3_2_0/modules/i2c_master_bit_ctrl.vhd