Mainly, the build system changes consist in organizing the makefile better and
building to a local `ubuntu/' folder, which should then be copied directly to
the PTS system.

Then, the flash test changes consist in checking for a BusException error to not
fall in the trap of continuing on other exceptions occuring in the block of code
under `try'. Also, the flash test is more "modular" in that the gateware
versions to be downloaded can be specified at the beginning of the file.

This was necessary because there is an error in the schematics of the V2-0
cards, which has the nets for these two LEDs swapped versus the PCB. The error
will be corrected on the schematics level, and here we swap as well to have them
correctly mapped per the PCB.

Not yet synthesized

This commit:
- adds rs485_pulse.py test script
- adds corresponding bits in ptsdefine.py
- adds the test in the Makefile

This commit:
- adds logic for the RS-485 test (both in top-level and in pts_regs)
- changes names of bits in pts_regs to generate shorter names in the doc

The V2 card has the front-panel LEDs non-negated (the Schmitt-trigger inverters
have been removed) and has LEDs added for each inverter channel. The relevant
changes have been made in this respect as follows:
- changed signal names in UCF and top-level VHDL file
- changed polarity of pulse LED outputs to active-high
- added the inverter LED outputs
- added the inverter LEDs in the LED sequencing scheme for the LED test

This is done to avoid an unnecessary 5 mins wasted on writing the bitstream,
even though we need to re-run the tests due to a failure.

The changes are listed below:
- added CRC calculation on reading of unique ID, to avoid writing an erroneous
  one in the log file and ultimately the MTF database
- aestaethic changes in the code (e.g., spaces added after 'if' statements)
- made the storage of the unique ID always be 16 characters long

This function now returns more Linux-oriented error codes (0 is success, 2 is
failure)

The following changes have been made to improve test script outputs:
- add numbers of ICs to test
- change CONV-TTL-BLO for CONV-TTL-RS485 where appropriate (the former was there
  because the scripts were imported from the CONV-TTL-BLO PTS)
- TTL pulse test: clearer output, indicating the channels and the ICs to check
  in case of error

An addition has been made in the top-level file to not run the tests if the
output of xc3sprog is not the expected one. This prevents blindly running the
tests on no gateware downloaded to the FPGA, and thus prevents wasted time.

The issue was an error in the schematics, where the names of the SDA line and
the RATE_SELECT lines were swapped. This led to the definitions of the pins in
the UCF file to be wrong and the SFP test not working.

With the proper pin names in the UCF file, the SFP test now works.

As mentioned in the previous commit, the SFP EEPROM test is not yet working.
Still under investigation as to why.

The EEPROM test doesn't work yet, but that may be related to the wrong-ish SFP
connector placed on the board.

Lengthy clarification: the PTS for the CONV-TTL-RS485 boards is inspired from
the PTS of CONV-TTL-BLO, where an SFP+ connector is used. Since the
CONV-TTL-RS485 uses just an SFP connector (not the SFP+), there might be
something wrong when reading the I2C interface. Reading the manuals yielded no
relevant reasons why this would occur, but I'm still investigating.

Either way, the link up test works, just the EEPROM test needs to be clarified
why it doesn't work. And the SFP changed for an SFP+.