hdl: Work towards RS-485 test

This commit: - adds logic for the RS-485 test (both in top-level and in pts_regs) - changes names of bits in pts_regs to generate shorter names in the doc

hdl: Work towards RS-485 test
This commit: - adds logic for the RS-485 test (both in top-level and in pts_regs) - changes names of bits in pts_regs to generate shorter names in the doc
23f8c0c5 · Theodor-Adrian Stana · ffba3aca · 23f8c0c5 · 23f8c0c5 · 23f8c0c5
Commit 23f8c0c5 authored Nov 11, 2014 by Theodor-Adrian Stana
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Showing with 423 additions and 77 deletions

pts_regs.vhd hdl/modules/pts_regs.vhd +102 -45

pts_regs.wb hdl/modules/pts_regs.wb +156 -8

pts.vhd hdl/top/pts.vhd +165 -24

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--- a/hdl/modules/pts_regs.vhd
+++ b/hdl/modules/pts_regs.vhd
--- a/hdl/modules/pts_regs.wb
+++ b/hdl/modules/pts_regs.wb
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- CONV-TTL-RS485 PTS registers wbgen2 description file
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- version: 1.0
+--
+-- description:
+--    This file contains the register description for the converter board
+--    registers and is to be used as input to the wbgen2 tool for generating
+--    an appropriate VHDL file.
+--
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    11-11-2014   Theodor Stana     Added GPL header
+--==============================================================================
+-- TODO: -
+--==============================================================================
+
 peripheral {
  name        = "PTS control and status registers";
  description = "Registers of the PTS firmware";
@@ -27,7 +60,7 @@ peripheral {

    field {
      name = "Front pulse LED enable";
-      prefix = "front_led_en";
+      prefix = "fledt";
      description = "1 -- Enable front panel LED sequencing \ 0 -- No effect";
      type = BIT;
      access_bus = READ_WRITE;
@@ -36,7 +69,7 @@ peripheral {

    field {
      name = "Rear pulse LED enable";
-      prefix = "rear_led_en";
+      prefix = "rledt";
      description = "1 -- Enable rear panel LED sequencing \ 0 -- No effect";
      type = BIT;
      access_bus = READ_WRITE;
@@ -45,7 +78,7 @@ peripheral {

    field {
      name = "Status LED enable";
-      prefix = "stat_led_en";
+      prefix = "stledt";
      description = "1 -- Enable front panel bicolor LED sequencing \ 0 -- No effect";
      type = BIT;
      access_bus = READ_WRITE;
@@ -53,8 +86,8 @@ peripheral {
    };

    field {
-      name = "TTL pulse enable";
-      prefix = "ttl_en";
+      name = "TTL test enable";
+      prefix = "ttlpt";
      description = "1 -- Enable pulse generation from CH1 \ 0 -- No effect";
      type = BIT;
      access_bus = READ_WRITE;
@@ -62,14 +95,50 @@ peripheral {
    };

    field {
-      name = "Rear pulse enable";
-      prefix = "rear_en";
-      description = "1 -- Enable rear pulse generation \ 0 -- No effect";
+      name = "RS485 pulse enable";
+      prefix = "rs485pt";
+      description = "1 -- Enable RS485 pulse generation \ 0 -- No effect";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

+    field {
+      name = "RS485 tester card VCC";
+      prefix = "tstcvcc";
+      description = "1 -- Power on the RS485 tester \ 0 -- No effect";
+      type = BIT;
+      access_bud = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "RS485 tester card MUX enable";
+      prefix = "tstcmuxen";
+      description = "1 -- Enable multiplexers on RS485 tester \ 0 -- No effect";
+      type = BIT;
+      access_bud = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "RS485 tester card MUX S0 line";
+      prefix = "tstcs0";
+      description = "RS485 tester S0 line on multiplexers";
+      type = BIT;
+      access_bud = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "RS485 tester card MUX S1 line";
+      prefix = "tstcs1";
+      description = "RS485 tester S1 line on multiplexers";
+      type = BIT;
+      access_bud = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
    field {
      name = "Reset unlock bit";
      description = "1 -- Reset bit unlocked \ 0 -- Reset bit locked";
@@ -136,4 +205,83 @@ peripheral {
    };
  };

+  reg {
+    name = "LSR";
+    description = "Line Status Register";
+    prefix = "lsr";
+    field {
+      name = "Front panel channel input state";
+      description = "Line state at board input\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "front";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "Front panel INV-TTL input state";
+      description = "Line state at board input\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "frontinv";
+      type = SLV;
+      size = 4;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "Rear panel input state";
+      description = "Line state at board input\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "rear";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "Front panel input failsafe state";
+      description = "High if line is in failsafe mode (e.g., no cable plugged in)\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "frontfs";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "Front panel inverter input failsafe state";
+      description = "High if line is in failsafe mode (e.g., no cable plugged in)\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "frontinvfs";
+      type = SLV;
+      size = 4;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+
+    field {
+      name = "Rear panel input failsafe state";
+      description = "High if line is in failsafe mode (e.g., no cable plugged in)\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "rearfs";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+  };
+
 };
--- a/hdl/top/pts.vhd
+++ b/hdl/top/pts.vhd