hdl: Work on adding I/O termination enable signals

Not yet synthesized

hdl: Work on adding I/O termination enable signals
Not yet synthesized
f8bff072 · Theodor-Adrian Stana · e9f17c9a · f8bff072 · f8bff072 · f8bff072
Commit f8bff072 authored Nov 12, 2014 by Theodor-Adrian Stana
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Showing with 123 additions and 10 deletions

pts_regs.vhd hdl/modules/pts_regs.vhd +43 -2

pts_regs.wb hdl/modules/pts_regs.wb +33 -0

pts.ucf hdl/top/pts.ucf +35 -6

pts.vhd hdl/top/pts.vhd +12 -2

No files found.
--- a/hdl/modules/pts_regs.vhd
+++ b/hdl/modules/pts_regs.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : pts_regs.vhd
 -- Author         : auto-generated by wbgen2 from pts_regs.wb
-- Created        : Tue Nov 11 15:12:09 2014
+-- Created        : Wed Nov 12 10:26:43 2014
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
@@ -78,7 +78,11 @@ entity pts_regs is
 -- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
    pts_lsr_frontinvfs_i                     : in     std_logic_vector(3 downto 0);
 -- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
-    pts_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0)
+    pts_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
+-- Port for std_logic_vector field: 'Input termination enable' in reg: 'TER'
+    pts_ter_iterm_o                          : out    std_logic_vector(5 downto 0);
+-- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER'
+    pts_ter_oterm_o                          : out    std_logic_vector(5 downto 0)
  );
 end pts_regs;

@@ -93,6 +97,8 @@ signal pts_csr_tstcvcc_int                      : std_logic      ;
 signal pts_csr_tstcmuxen_int                    : std_logic      ;
 signal pts_csr_tstcs0_int                       : std_logic      ;
 signal pts_csr_tstcs1_int                       : std_logic      ;
+signal pts_ter_iterm_int                        : std_logic_vector(5 downto 0);
+signal pts_ter_oterm_int                        : std_logic_vector(5 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
@@ -133,6 +139,8 @@ begin
      pts_csr_rst_load_o <= '0';
      pts_csr_i2c_err_load_o <= '0';
      pts_csr_i2c_wdto_load_o <= '0';
+      pts_ter_iterm_int <= "000000";
+      pts_ter_oterm_int <= "000000";
    elsif rising_edge(clk_sys_i) then
 -- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
@@ -208,6 +216,35 @@ begin
            rddata_reg(31 downto 26) <= pts_lsr_rearfs_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
+          when "11" => 
+            if (wb_we_i = '1') then
+              pts_ter_iterm_int <= wrdata_reg(5 downto 0);
+              pts_ter_oterm_int <= wrdata_reg(11 downto 6);
+            end if;
+            rddata_reg(5 downto 0) <= pts_ter_iterm_int;
+            rddata_reg(11 downto 6) <= pts_ter_oterm_int;
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
          when others =>
 -- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
@@ -256,6 +293,10 @@ begin
 -- Front panel input failsafe state
 -- Front panel inverter input failsafe state
 -- Rear panel input failsafe state
+-- Input termination enable
+  pts_ter_iterm_o <= pts_ter_iterm_int;
+-- Output termination enable
+  pts_ter_oterm_o <= pts_ter_oterm_int;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
 -- ACK signal generation. Just pass the LSB of ACK counter.

--- a/hdl/modules/pts_regs.wb
+++ b/hdl/modules/pts_regs.wb
@@ -56,6 +56,7 @@ peripheral {
  -- Control & Status Register
  reg {
    name = "CSR";
+    description = "Control and Status Register";
    prefix = "csr";

    field {
@@ -284,4 +285,36 @@ peripheral {
    };
  };

+  reg {
+    name = "TER";
+    description = "Termination Enable Register";
+    prefix = "ter";
+
+    field {
+      name = "Input termination enable";
+      description = "Set high to enable the channel input termination\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "iterm";
+      type = SLV;
+      size = 6;
+      access_dev = READ_ONLY;
+      access_bus = READ_WRITE;
+    };
+
+    field {
+      name = "Output termination enable";
+      description = "Set high to enable the channel output terminations\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "oterm";
+      type = SLV;
+      size = 6;
+      access_dev = READ_ONLY;
+      access_bus = READ_WRITE;
+    };
+  };
+
 };
--- a/hdl/top/pts.ucf
+++ b/hdl/top/pts.ucf
@@ -203,6 +203,35 @@ NET "rs485_fs_n_i[4]" IOSTANDARD = LVCMOS33;
 NET "rs485_fs_n_i[5]" LOC = AB7;
 NET "rs485_fs_n_i[5]" IOSTANDARD = LVCMOS33;

+#------------------------------------------------------------------------------
+# Input and output termination enable lines
+#------------------------------------------------------------------------------
+NET "iterm_en_o[0]" LOC = W14;
+NET "iterm_en_o[0]" IOSTANDARD = LVCMOS33;
+NET "iterm_en_o[1]" LOC = W13;
+NET "iterm_en_o[1]" IOSTANDARD = LVCMOS33;
+NET "iterm_en_o[2]" LOC = W12;
+NET "iterm_en_o[2]" IOSTANDARD = LVCMOS33;
+NET "iterm_en_o[3]" LOC = W11;
+NET "iterm_en_o[3]" IOSTANDARD = LVCMOS33;
+NET "iterm_en_o[4]" LOC = W10;
+NET "iterm_en_o[4]" IOSTANDARD = LVCMOS33;
+NET "iterm_en_o[5]" LOC = W9;
+NET "iterm_en_o[5]" IOSTANDARD = LVCMOS33;
+
+NET "oterm_en_o[0]" LOC = T22;
+NET "oterm_en_o[0]" IOSTANDARD = LVCMOS33;
+NET "oterm_en_o[1]" LOC = T21;
+NET "oterm_en_o[1]" IOSTANDARD = LVCMOS33;
+NET "oterm_en_o[2]" LOC = T20;
+NET "oterm_en_o[2]" IOSTANDARD = LVCMOS33;
+NET "oterm_en_o[3]" LOC = U20;
+NET "oterm_en_o[3]" IOSTANDARD = LVCMOS33;
+NET "oterm_en_o[4]" LOC = V20;
+NET "oterm_en_o[4]" IOSTANDARD = LVCMOS33;
+NET "oterm_en_o[5]" LOC = W20;
+NET "oterm_en_o[5]" IOSTANDARD = LVCMOS33;
+
 #------------------------------------------------------------------------------
 # Channel LEDs
 #------------------------------------------------------------------------------
@@ -284,18 +313,18 @@ NET "vme_ga_i[4]" IOSTANDARD = LVCMOS33;
 #-----------------------------------------------------------------------------
 # DAC control
 #-----------------------------------------------------------------------------
-NET "dac_20_din_o" LOC = AB14;
+NET "dac_20_din_o" LOC = AB13;
 NET "dac_20_din_o" IOSTANDARD = LVCMOS33;
-NET "dac_20_sclk_o" LOC = AA14;
+NET "dac_20_sclk_o" LOC = Y13;
 NET "dac_20_sclk_o" IOSTANDARD = LVCMOS33;
-NET "dac_20_sync_n_o" LOC = AB15;
+NET "dac_20_sync_n_o" LOC = AB14;
 NET "dac_20_sync_n_o" IOSTANDARD = LVCMOS33;

-NET "dac_125_din_o" LOC = W14;
+NET "dac_125_din_o" LOC = Y14;
 NET "dac_125_din_o" IOSTANDARD = LVCMOS33;
-NET "dac_125_sclk_o" LOC = Y14;
+NET "dac_125_sclk_o" LOC = AA14;
 NET "dac_125_sclk_o" IOSTANDARD = LVCMOS33;
-NET "dac_125_sync_n_o" LOC = W13;
+NET "dac_125_sync_n_o" LOC = AB15;
 NET "dac_125_sync_n_o" IOSTANDARD = LVCMOS33;

 #-----------------------------------------------------------------------------

--- a/hdl/top/pts.vhd
+++ b/hdl/top/pts.vhd
@@ -88,6 +88,10 @@ entity pts is
    rs485_fs_n_i            : in  std_logic_vector(5 downto 0);
    rs485_o                 : out std_logic_vector(5 downto 0);

+    -- Rear input and output termination lines
+    iterm_en_o              : out std_logic_vector(5 downto 0);
+    oterm_en_o              : out std_logic_vector(5 downto 0);
+
    -- Channel leds
    led_front_o             : out std_logic_vector(5 downto 0);
    led_inv_o               : out std_logic_vector(3 downto 0);
@@ -313,7 +317,11 @@ architecture arch of pts is
  -- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
      pts_lsr_frontinvfs_i                     : in     std_logic_vector(3 downto 0);
  -- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
-      pts_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0)
+      pts_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
+  -- Port for std_logic_vector field: 'Input termination enable' in reg: 'TER'
+      pts_ter_iterm_o                          : out    std_logic_vector(5 downto 0);
+  -- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER'
+      pts_ter_oterm_o                          : out    std_logic_vector(5 downto 0)
    );
  end component pts_regs;

@@ -952,7 +960,9 @@ begin
      pts_lsr_rear_i            => line_rear,
      pts_lsr_frontfs_i         => (others => '0'),
      pts_lsr_frontinvfs_i      => (others => '0'),
-      pts_lsr_rearfs_i          => line_rear_fs
+      pts_lsr_rearfs_i          => line_rear_fs,
+      pts_ter_iterm_o           => iterm_en_o,
+      pts_ter_oterm_o           => oterm_en_o
    );

  -- Implement the RST_UNLOCK bit