Commit d5eaab04 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

sw: Work towards RS-485 test

This commit:
- adds rs485_pulse.py test script
- adds corresponding bits in ptsdefine.py
- adds the test in the Makefile
parent 23f8c0c5
......@@ -23,6 +23,7 @@ all:
cp python/dac_vcxo_pll.py pts-conv-ttl-rs485/tests/
cp python/therm_id.py pts-conv-ttl-rs485/tests/
cp python/ttl_pulse_switch.py pts-conv-ttl-rs485/tests/
cp python/rs485_pulse.py pts-conv-ttl-rs485/tests/
cp python/sfp_eeprom.py pts-conv-ttl-rs485/tests/
cp python/sfp_test.py pts-conv-ttl-rs485/tests/
cp python/flashtest.py pts-conv-ttl-rs485/
......@@ -30,13 +31,14 @@ all:
ln -s tests/dac_vcxo_pll.py pts-conv-ttl-rs485/test01.py
ln -s tests/leds.py pts-conv-ttl-rs485/test02.py
ln -s tests/ttl_pulse_switch.py pts-conv-ttl-rs485/test03.py
ln -s tests/rs485_pulse.py pts-conv-ttl-rs485/test04.py
ln -s tests/therm_id.py pts-conv-ttl-rs485/test05.py
ln -s tests/sfp_eeprom.py pts-conv-ttl-rs485/test06.py
ln -s tests/sfp_test.py pts-conv-ttl-rs485/test07.py
wget -P pts-conv-ttl-rs485/boot http://www.ohwr.org/attachments/download/3648/pts.bit
wget -P pts-conv-ttl-rs485/boot http://www.ohwr.org/attachments/download/3668/pts.bit
wget -P pts-conv-ttl-rs485/boot http://www.ohwr.org/attachments/download/3650/flash_load.bit
wget -P pts-conv-ttl-rs485/boot http://www.ohwr.org/attachments/download/3649/golden-v0.0_release-v1.0.bin
wget -P pts-conv-ttl-rs485/boot http://www.ohwr.org/attachments/download/3657/golden-v0.0_release-v1.0.bin
clean:
rm -rf pts-conv-ttl-rs485
......
......@@ -50,14 +50,25 @@ BIDR = 0x000
BIDR_ARR = [ "TBLO", "T485" ]
# Control and Status Register
CSR = 0x004
CSR_FRONT_LED_EN_OFS = 0
CSR_REAR_LED_EN_OFS = 1
CSR_STAT_LED_EN_OFS = 2
CSR_TTL_EN_OFS = 3
CSR_REAR_EN_OFS = 4
CSR_RST_UNLOCK_OFS = 14
CSR_RST_OFS = 15
CSR = 0x004
CSR_FRONT_LED_EN_OFS = 0
CSR_REAR_LED_EN_OFS = 1
CSR_STAT_LED_EN_OFS = 2
CSR_TTL_EN_OFS = 3
CSR_REAR_EN_OFS = 4
CSR_TESTER_VCC_OFS = 5
CSR_TESTER_MUX_EN_OFS = 6
CSR_TESTER_MUX_S0_OFS = 7
CSR_TESTER_MUX_S1_OFS = 8
CSR_RST_UNLOCK_OFS = 14
CSR_RST_OFS = 15
# Line Status Register
LSR = 0x008
LSR_FRONT_OFS = 0
LSR_FRONTINV_OFS = 6
LSR_REAR_OFS = 10
LSR_REARFS_OFS = 26
# 1-Wire base address, used in therm_id.py
TEMP_1WIRE_BASE = 0x010
......
# Import system modules
import sys
sys.path.append("../lib/")
import time
# Import common modules
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
class CPulseCounter:
def __init__(self, bus, base):
self.bus = bus
self.base = base
def wr_reg(self, addr, val):
self.bus.vv_write(self.base + addr,val)
def rd_reg(self, addr):
return self.bus.vv_read(self.base + addr)
def wr_out_cnt(self, chan, val):
return self.wr_reg((chan-1)*8, val)
def wr_in_cnt(self, chan, val):
return self.wr_reg((chan-1)*8 + 4, val)
def rd_out_cnt(self, chan):
return self.rd_reg((chan-1)*8)
def rd_in_cnt(self, chan):
return self.rd_reg((chan-1)*8 + 4)
def mux_sel(bus, sel):
val = bus.vv_read(CSR)
val &= ~(1 << CSR_TESTER_MUX_S0_OFS)
val &= ~(1 << CSR_TESTER_MUX_S1_OFS)
if (sel & 0x1):
val |= (1 << CSR_TESTER_MUX_S0_OFS)
if (sel & 0x2):
val |= (1 << CSR_TESTER_MUX_S1_OFS)
bus.vv_write(CSR, val)
def en_pulse_gen(bus):
val = bus.vv_read(CSR)
val |= (1 << CSR_REAR_EN_OFS)
bus.vv_write(CSR, val)
def dis_pulse_gen(bus):
val = bus.vv_read(CSR)
val &= ~(1 << CSR_REAR_EN_OFS)
bus.vv_write(CSR, val)
def clear_counters(pc):
# Clear pulse counters for the TTL channels
for i in range(11, 17):
pc.wr_out_cnt(i, 0)
pc.wr_in_cnt(i, 0)
def check_counters(pc, inf, pel):
ic_arr = []
oc_arr = []
for i in range(11, 17):
ic_arr.append(pc.rd_in_cnt(i))
oc_arr.append(pc.rd_out_cnt(i))
for i in range(len(ic_arr)):
if (ic_arr[i] == oc_arr[i]):
msg = "Ch%d input counter (%d) matches the output counter (%d) - good\n" % (i+1,
ic_arr[i], oc_arr[i])
inf.write(msg)
else:
msg = "ERROR: Ch%d input counter (%d) does not match output counter (%d)"% (i+1,
ic_arr[i], oc_arr[i])
pel.set(msg)
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus, tname, inf, log):
"""
tests : RS-485 pulse repetition, RS-485 transceivers IC31-IC56,
solid-state switches IC56-IC75, solid-state switches
IC23-IC28, RS-485 transceivers IC16-IC21, Schmitt trigger
inputs IC30, IC45, NAND gate IC8
uses : pts.bit and rs485_pulse.py
"""
pel = PTS_ERROR_LOGGER(inf, log)
try:
# Initialize a pulse counter object
pc = CPulseCounter(bus, PULSE_CNT_BASE)
clear_counters(pc)
# Ask the user to make the daisy-chain
print("Connect the LEMO cable as follows:")
print(" - BLU cable to INV-TTL CH A")
print(" - GRN cable to INV-TTL CH B")
print(" - RED cable to INV-TTL CH C")
print(" - YEL cable to INV-TTL CH D")
reply = raw_input("Have the connections been made? (yes/no) ")
while (1):
if "yes" in reply.lower():
break
if "no" in reply.lower():
msg = "ERROR: Control connections to RS485 tester not made"
pel.set(msg)
else:
reply = raw_input('Please type "yes" or "no" to continue: ')
# Power on the tester card
val = bus.vv_read(CSR)
val |= (1 << CSR_TESTER_VCC_OFS)
bus.vv_write(CSR, val)
# Read out fail-safe lines -- should now be high, since the MUXes are
# powered but not enabled
val = bus.vv_read(LSR)
val >>= LSR_REARFS_OFS
if (val == 0x3f):
msg = "RS-485 failsafe lines read as expected: 0x%02X\n" % val
inf.write(msg)
else:
msg = "ERROR: Failsafe lines readout (0x%02X) incorrect - expected 0x3F" % val
pel.set(msg)
# Enable multiplexer
print("Enabling multiplexers")
val = bus.vv_read(CSR)
val |= (1 << CSR_TESTER_MUX_EN_OFS)
bus.vv_write(CSR, val)
# Generate pulses from different outputs to inputs
msg = "Testing channel connections: O1 -> I"
print(msg)
mux_sel(bus, 0x0)
inf.write(msg+'\n')
en_pulse_gen(bus)
time.sleep(2)
dis_pulse_gen(bus)
check_counters(pc, inf, pel)
clear_counters(pc)
msg = "Testing channel connections: O2 -> I"
print(msg)
mux_sel(bus, 0x1)
inf.write(msg+'\n')
en_pulse_gen(bus)
time.sleep(2)
dis_pulse_gen(bus)
check_counters(pc, inf, pel)
clear_counters(pc)
msg = "Testing channel connections: O3 -> I"
print(msg)
mux_sel(bus, 0x2)
inf.write(msg+'\n')
en_pulse_gen(bus)
time.sleep(2)
dis_pulse_gen(bus)
check_counters(pc, inf, pel)
clear_counters(pc)
msg = "Testing fail-safe"
print(msg)
mux_sel(bus, 0x3)
inf.write(msg+'\n')
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % e)
except BusWarning, e:
raise PtsError("SKT Warning: %s" % e)
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