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Conv TTL RS485 - Testing
Commit 22fb2160 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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sw: Improved output of test scripts 

The following changes have been made to improve test script outputs:
- add numbers of ICs to test
- change CONV-TTL-BLO for CONV-TTL-RS485 where appropriate (the former was there
  because the scripts were imported from the CONV-TTL-BLO PTS)
- TTL pulse test: clearer output, indicating the channels and the ICs to check
  in case of error
parent 7f121843
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Showing with 59 additions and 53 deletions
pts/python/dac_vcxo_pll.py
View file @ 22fb2160
##________________________________________________________________________________________________
##
## CONV-TTL-BLO PTS
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##________________________________________________________________________________________________
##
##------------------------------------------------------------------------------------------------
##
## CONV-TTL-BLO DAC, VCXO, PLL test
## CONV-TTL-RS485 DAC, VCXO, PLL test
##
##------------------------------------------------------------------------------------------------
##
......@@ -24,10 +24,10 @@
## ------|__________| |________|
## __________ ________ ________
## ------| | | | | |
## SPI ------| DAC_PLL |----->| OSC |----->|PLL ICPLLBLAH|----> PLL 125 MHz clk
## SPI ------| DAC_PLL |----->| OSC |----->| PLL |----> PLL 125 MHz clk
## ------|__________| |________| |________|
##
## The firmware loaded to the FPGA implements the interface for the communication
## The gateware loaded to the FPGA implements the interface for the communication
## between the DACs and the I2C bus on the VME P1 connector. The DAC interface is an
## SPI Wishbone master, running at a system clock of 20MHz. The SPI Wishbone master
## for the DAC_VCXO can be accessed at base address 0x080. The SPI Wishbone master
......@@ -171,7 +171,7 @@ class COpenCoresSPI:
tmp = (self.rd_reg(self.R_CTRL) >> 8) & 0x00000001
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: DAC DACBLAH or ICDACBLAH: Not responding"
msg = "ERROR: DAC IC52 or IC53: Not responding"
raise PtsError(msg)
return txrx
......@@ -217,7 +217,7 @@ class DAC_AD5662:
def main(bus,tname,inf,log):
"""
tests : DAC DACBLAH, VCXO OSCBLAH, DAC ICDACBLAH, VCXO OSCBLAHBLAH, PLL ICPLLBLAH
tests : DAC IC52, VCXO OSC3, DAC IC53, VCXO OSC1, PLL IC29
uses : pts.bit and dac_vcxo_pll.py
"""
......@@ -250,41 +250,41 @@ def main(bus,tname,inf,log):
# Resetting VCXO & PLL Counters
bus.vv_write(VCXO_CLKINFO_BASE + CLKINFO_RST_OFS, 1) # Reset VCXO counter
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_RST_OFS, 1) # Reset PLL ICPLLBLAH counter
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_RST_OFS, 1) # Reset PLL IC29 counter
vcxo_count = bus.vv_read(VCXO_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read VCXO counter, counter is under reset
pll125_count = bus.vv_read(PLL_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read PLL ICPLLBLAH counter, counter is under reset
pll125_count = bus.vv_read(PLL_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read PLL IC29 counter, counter is under reset
# Enabling VCXO & PLL Counters
bus.vv_write(VCXO_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 1) # Enable VCXO counter
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 1) # Enable PLL ICPLLBLAH counter
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 1) # Enable PLL IC29 counter
bus.vv_write(VCXO_CLKINFO_BASE + CLKINFO_RST_OFS, 0) # Release VCXO counter reset
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_RST_OFS, 0) # Release PLL ICPLLBLAH counter reset
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_RST_OFS, 0) # Release PLL IC29 counter reset
# VCXO & PLL Counters counting for 2 secs..
time.sleep(2)
bus.vv_write(VCXO_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 0) # Disable VCXO counter
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 0) # Disable PLL ICPLLBLAH counter
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 0) # Disable PLL IC29 counter
# Reading VCXO & PLL Counters
vcxo_count = bus.vv_read(VCXO_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read VCXO counter
pll125_count = bus.vv_read(PLL_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read PLL ICPLLBLAH counter
pll125_count = bus.vv_read(PLL_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read PLL IC29 counter
vcxo.append(vcxo_count)
pll125.append(pll125_count)
# Evaluating the VCXO and PLL clock frequencies at DAC middle value 1.65
if dac_volt == 1.65:
if (vcxo_count > (VCXO_COUNTER_2SEC-VCXO_COUNTER_MARGIN)) and (vcxo_count < (VCXO_COUNTER_2SEC+VCXO_COUNTER_MARGIN)):
msg = "VCXO OSCBLAH: Frequency OK; Counter value after 2sec: %d is within range[%d .. %d]" % (vcxo_count, VCXO_COUNTER_2SEC-VCXO_COUNTER_MARGIN, VCXO_COUNTER_2SEC+VCXO_COUNTER_MARGIN)
msg = "VCXO OSC3: Frequency OK; Counter value after 2sec: %d is within range[%d .. %d]" % (vcxo_count, VCXO_COUNTER_2SEC-VCXO_COUNTER_MARGIN, VCXO_COUNTER_2SEC+VCXO_COUNTER_MARGIN)
inf.write("%s\n" % (msg))
else:
msg = "ERROR: VCXO OSCBLAH: Wrong frequency; Counter value after 2sec: %d out of range[%d .. %d]" % (vcxo_count, VCXO_COUNTER_2SEC-VCXO_COUNTER_MARGIN, VCXO_COUNTER_2SEC+VCXO_COUNTER_MARGIN)
msg = "ERROR: VCXO OSC3: Wrong frequency; Counter value after 2sec: %d out of range[%d .. %d]" % (vcxo_count, VCXO_COUNTER_2SEC-VCXO_COUNTER_MARGIN, VCXO_COUNTER_2SEC+VCXO_COUNTER_MARGIN)
pel.set(msg)
if (pll125_count > (PLL_COUNTER_2SEC-PLL_COUNTER_MARGIN)) and (pll125_count < (PLL_COUNTER_2SEC+PLL_COUNTER_MARGIN)):
msg = "PLL ICPLLBLAH: Frequency OK; Counter value after 2sec: %d is within range[%d .. %d]" % (pll125_count, PLL_COUNTER_2SEC-PLL_COUNTER_MARGIN, PLL_COUNTER_2SEC+PLL_COUNTER_MARGIN)
msg = "PLL IC29: Frequency OK; Counter value after 2sec: %d is within range[%d .. %d]" % (pll125_count, PLL_COUNTER_2SEC-PLL_COUNTER_MARGIN, PLL_COUNTER_2SEC+PLL_COUNTER_MARGIN)
inf.write("%s\n" % (msg))
else:
msg = "ERROR: PLL ICPLLBLAH: Wrong frequency; Counter value after 2sec: %d out of range[%d .. %d]" % (pll125_count, PLL_COUNTER_2SEC-PLL_COUNTER_MARGIN, PLL_COUNTER_2SEC+PLL_COUNTER_MARGIN)
msg = "ERROR: PLL IC29: Wrong frequency; Counter value after 2sec: %d out of range[%d .. %d]" % (pll125_count, PLL_COUNTER_2SEC-PLL_COUNTER_MARGIN, PLL_COUNTER_2SEC+PLL_COUNTER_MARGIN)
pel.set(msg)
inf.write("\n")
......@@ -295,9 +295,9 @@ def main(bus,tname,inf,log):
if i > 0:
diff = grad - ograd
if diff < 0:
inf.write("VCXO OSCBLAH: Frequency responds to change in DAC DACBLAH OK. DAC=%3.2fV\n" % (dac_volts[i]))
inf.write("VCXO OSC3: Frequency responds to change in DAC IC52 OK. DAC=%3.2fV\n" % (dac_volts[i]))
else:
msg = "ERROR: VCXO OSCBLAH: Frequency not responding to change in DAC DACBLAH control value"
msg = "ERROR: VCXO OSC3: Frequency not responding to change in DAC IC52 control value"
pel.set(msg)
ograd = grad
......@@ -308,9 +308,9 @@ def main(bus,tname,inf,log):
if i > 0:
diff = grad - ograd
if diff < 0:
inf.write("PLL ICPLLBLAH: Frequency responds to change in DAC ICDACBLAH OK. DAC=%3.2fV\n" % (dac_volts[i]))
inf.write("PLL IC29: Frequency responds to change in DAC IC53 OK. DAC=%3.2fV\n" % (dac_volts[i]))
else:
msg = "ERROR: PLL ICPLLBLAH: Frequency not responding to change in DAC ICDACBLAH control value"
msg = "ERROR: PLL IC29: Frequency not responding to change in DAC IC53 control value"
pel.set(msg)
ograd = grad
......
pts/python/jpts.py
View file @ 22fb2160
......@@ -217,10 +217,10 @@ if __name__ == '__main__':
try:
# First load a firmware and read back a register to confirm correct load.
if bus.vv_load()==1:
msg = "INFO:Found CONV-TTL-RS485 board in slot:%d OK\n" % (lun)
msg = "INFO: Found CONV-TTL-RS485 board in slot %d\n" % (lun)
inf.write(msg + '\n')
# Each test is passed the test name, the log and info files and the
# Each test is passed the test name, the log and info files and the
# bus object. The test program is expected to return the number of
# errors that occured. If no errors occur, the test PASSes, otherwise
# it FAILs.
......
pts/python/leds.py
View file @ 22fb2160
......@@ -17,7 +17,7 @@
## For this test, the operator's intervention is needed; when prompted, the operator
## needs to visually check the LEDS.
##
## The FPGA firmware sequences through each of the front panel LEDs (pulse LEDs
## The FPGA gateware sequences through each of the front panel LEDs (pulse LEDs
## status LEDs) based on the value of the current test field in the PTS control
## register. In order to start and stop LED sequencing, the test sets and clears
## control bits in the PTS CSR.
......@@ -66,7 +66,7 @@ from ptsdefine import *
def main(bus,tname,inf,log):
"""
tests : Front Panel LEDs with Schmitt trigger driver ICxxx, bicolor LEDs with transceiver ICxx
tests : Front Panel LEDs, bicolor LEDs with transceiver IC1
"""
pel = PTS_ERROR_LOGGER(inf,log)
......@@ -76,14 +76,14 @@ def main(bus,tname,inf,log):
# First phase of LED test, enable pulse LED sequencing
bus.vv_write(CSR, 1 << CSR_FRONT_LED_EN_OFS)
# The firmware should blink the LEDs, ask the operator for input
# The gateware should blink the LEDs, ask the operator for input
inp = raw_input("--> Are the channel LEDs blinking one by one? yes/no: ")
while True:
if inp.find("yes") != -1 or inp.find("YES") != -1:
break
if inp.find("no") != -1 or inp.find("NO") != -1:
msg = "ERROR: Front Panel LEDs or Schmitt trigger ICxxx"
msg = "ERROR: Front Panel LEDs"
pel.set(msg)
break
......@@ -92,14 +92,14 @@ def main(bus,tname,inf,log):
# Second phase of LED test, enable status LED sequencing
bus.vv_write(CSR, 1 << CSR_STAT_LED_EN_OFS)
# The firmware should blink the LEDs, ask the operator for input
# The gateware should blink the LEDs, ask the operator for input
inp = raw_input("--> Are the status LEDs blinking one by one? yes/no: ")
while True:
if inp.find("yes") != -1 or inp.find("YES") != -1:
break
if inp.find("no") != -1 or inp.find("NO") != -1:
msg = "ERROR: Status LEDs or transceiver ICxxx"
msg = "ERROR: Status LEDs or transceiver IC1"
pel.set(msg)
break
......
pts/python/sfp_eeprom.py
View file @ 22fb2160
......@@ -11,7 +11,7 @@
##
##------------------------------------------------------------------------------------------------
##
## Description Testing of the SFP EEPROM chip on the CONV-TTL-RS485 board (SFP J1). The firmware
## Description Testing of the SFP EEPROM chip on the CONV-TTL-RS485 board (SFP J1). The gateware
## loaded to the on-board FPGA implements the interface for the communication
## between the I2C bus on the P1 VME connector and the I2C of the SFP EEPROM; the
## interface is an I2C Wishbone master, running on a 20 MHz system clock.
......@@ -113,7 +113,7 @@ class COpenCoresI2C:
while(self.rd_reg(self.R_SR) & self.SR_TIP):
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: SFP_EEPROM: Not responding"
msg = "ERROR: SFP-EEPROM: Not responding"
raise PtsError(msg)
def start(self, addr, write_mode):
......
pts/python/sfp_test.py
View file @ 22fb2160
......@@ -183,5 +183,3 @@ def main(bus,tname,inf,log):
except BusWarning, e:
raise PtsError("SKT Warning: %s" % (e))
#finally:
# return pel.get()
pts/python/therm_id.py
View file @ 22fb2160
......@@ -11,12 +11,12 @@
##
##------------------------------------------------------------------------------------------------
##
## Description Testing of the DS18B20 thermometer chip (ICxxx) on the CONV-TTL-RS-485 . The
## firmware loaded to the FPGA implements the interface for the communication between
## Description Testing of the DS18B20 thermometer chip (IC22) on the CONV-TTL-RS-485 . The
## gateware loaded to the FPGA implements the interface for the communication between
## the SKT bus and the one wire of the DS18B20; this interface a one wire Wishbone
## master, running on a 20 MHz system clock.
##
## The family code of the DS18B20 is x28, predefined in the part number.
## The family code of the DS18B20 is 0x28, predefined in the part number.
##
## The test reads the unique ID and the temperature and checks if the received
## values are within reasonable limits.
......@@ -102,7 +102,7 @@ class COpenCoresOneWire:
while(self.rd_reg(self.R_CSR) & self.CSR_CYC_MSK):
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: TempID ICxxx: Not responding"
msg = "ERROR: TempID IC22: Not responding"
raise PtsError(msg)
reg = self.rd_reg(self.R_CSR)
......@@ -115,7 +115,7 @@ class COpenCoresOneWire:
while(self.rd_reg(self.R_CSR) & self.CSR_CYC_MSK):
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: TempID ICxxx: Not responding"
msg = "ERROR: TempID IC22: Not responding"
raise PtsError(msg)
reg = self.rd_reg(self.R_CSR)
......@@ -185,12 +185,12 @@ class CDS18B20:
def read_serial_number(self):
if(1 != self.onewire.reset(self.port)):
msg = "ERROR: TempID ICxxx: Not responding"
msg = "ERROR: TempID IC22: Not responding"
raise PtsError(msg)
else:
err = self.onewire.write_byte(self.port, self.ROM_READ)
if err != 0:
msg = "ERROR: TempID ICxxx: Write failed"
msg = "ERROR: TempID IC22: Write failed"
raise PtsError(msg)
family_code = self.onewire.read_byte(self.port)
......@@ -203,7 +203,7 @@ class CDS18B20:
def access(self, serial_number):
if(1 != self.onewire.reset(self.port)):
msg = "ERROR: TempID ICxxx: Not responding"
msg = "ERROR: TempID IC22: Not responding"
raise PtsError(msg)
else:
err = self.onewire.write_byte(self.port, self.ROM_MATCH)
......@@ -235,7 +235,7 @@ class CDS18B20:
def main(bus,tname,inf,log):
"""
tests : Thermometer ICxxx and unique ID
tests : Thermometer IC22 and unique ID
uses : pts.bit and therm_id.py
"""
......@@ -251,7 +251,7 @@ def main(bus,tname,inf,log):
# Reading of unique ID
unique_id = ds18b20.read_serial_number()
if(unique_id == -1):
msg = "ERROR: TempID ICxxx: Unable to read 1-wire thermometer"
msg = "ERROR: TempID IC22: Unable to read 1-wire thermometer"
pel.set(msg)
else:
inf.write("Unique ID: %.12X\n" % (unique_id))
......@@ -262,12 +262,12 @@ def main(bus,tname,inf,log):
# Cheking if received values are reasonable
if temp < 10.0 or temp > 50.0:
msg = "ERROR: TempID ICxxx: Temperature: %d out of range[10 .. 50oC]" % (temp)
msg = "ERROR: TempID IC22: Temperature: %d out of range[10 .. 50oC]" % (temp)
pel.set(msg)
if((unique_id & 0xFF) != FAMILY_CODE):
family_code = unique_id & 0xFF
msg = "ERROR: TempID ICxxx: Invalid family code: 0x%.8X\n" % (family_code)
msg = "ERROR: TempID IC22: Invalid family code: 0x%.8X\n" % (family_code)
pel.set(msg)
return pel.get()
......
pts/python/ttl_pulse_switch.py
View file @ 22fb2160
......@@ -12,15 +12,15 @@
##-----------------------------------------------------------------------------------------------
##
## Description This module implements the TTL pulse repetition test. It tests TTL input Schmitt
## triggers IC6 (TTL) and IC11(INV-TTL), along with bus buffers IC2, IC3 and enable
## NAND gate IC10.
## triggers IC4 (TTL) and IC9(INV-TTL), along with bus buffers IC2, IC3 and enable
## NAND gate IC8.
##
## There are ten TTL pulse channels this test checks. Six (CH1-6) are TTL
## channels and four (CH6-10) are INV-TTL channels, but the FPGA firmware sends
## channels and four (CH6-10) are INV-TTL channels, but the FPGA gateware sends
## TTL pulses on all channels, since the PCB circuits for TTL and INV-TTL channels
## are the same.
##
## Counters are implemented in the firmware to count the number of pulses sent and
## Counters are implemented in the gateware to count the number of pulses sent and
## received on a channel. There are two counters per channel, one for input and
## one for output; the counters increment on the rising edge of a pulse signal. The
## current value of each counter can be read via a special Wishbone-mapped slave,
......@@ -143,13 +143,15 @@ class CPulseCounter:
def main(bus, tname, inf, log):
"""
tests : TTL pulse repetition, buffers ICxxx, ICxxx, Schmitt trigger
inputs ICxxx, ICxxx, NAND gate ICxxx
tests : TTL pulse repetition, buffers IC2, IC3, Schmitt trigger
inputs IC4, IC9, NAND gate IC8
uses : pts.bit and ttl_pulse_switch.py
"""
pel = PTS_ERROR_LOGGER(inf, log)
chans = ['1', '2', '3', '4', '5', '6', 'A', 'B', 'C', 'D']
try:
# Initialize a pulse counter object
pc = CPulseCounter(bus, PULSE_CNT_BASE)
......@@ -178,17 +180,23 @@ def main(bus, tname, inf, log):
# First, check for all-zeroes in counters, indicating enable NAND gate failure
if all(ic == 0 for ic in ic_arr):
msg = "ERROR: No pulses received, check enable NAND gate ICxxx"
msg = "ERROR: No pulses received - check daisy-chain, or enable NAND gate IC8"
pel.set(msg)
# Then, check if the number of pulses sent on the previous channel has
# been received correctly on the current channel
for i in range(0,10):
if (ic_arr[i] != 0) and (ic_arr[i] == oc_arr[i-1]):
msg = "CH%d received %d pulses and sent %d pulses - good\n" % (i+1, ic_arr[i], oc_arr[i])
msg = "Ch%s received %d pulses and sent %d pulses - good\n" % (chans[i], ic_arr[i], oc_arr[i])
inf.write(msg)
else:
msg = "ERROR: CH%d received %d pulses and sent %d pulses" % (i+1, ic_arr[i], oc_arr[i])
msg = "ERROR: Ch%s received %d pulses and sent %d pulses - " % (chans[i], ic_arr[i], oc_arr[i])
if (i == 0):
msg += "check daisy-chain, IC4 or IC2, or IC3"
elif (i < 6):
msg += "check daisy-chain, IC4 or IC2"
else:
msg += "check daisy-chain, IC9 or IC3"
pel.set(msg)
# Switches test
......
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