- 29 Apr, 2020 5 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
testbench/include: fix TDC EIC register addresses. THEY ARE BADLY GENERATED by WBGEN, if the driver uses a wbgen-produced .h file cross-check agains the .vh file in this commit!
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 24 Apr, 2020 6 commits
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Tomasz Wlostowski authored
- initialize TDC DMA Engine (buffer controller) - reset the SPEC/DDR contoller prior to operation (still wip) - feed the design with fake timestamps bypassing ACAM, let's debug one thing at a time. This is a WIP commit, I see the core writing the timestamps to the DDR, but the Gennum-side DMA as well as double-buffering of the DDR timestamps is yet to be implemented. Note: I've never managed to simulate DMA with the crappy Gennum VHDL model. I guess we need to fix it or write a new one..
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
wr_spec_tdc: expose sim_timestamp interface to feed fake timestamps to the core without modelling the ACAM chip
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Evangelia Gousiou authored
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- 22 Apr, 2020 3 commits
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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- 07 Apr, 2020 1 commit
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Evangelia Gousiou authored
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- 24 Mar, 2020 1 commit
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Evangelia Gousiou authored
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- 28 Feb, 2020 1 commit
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Evangelia Gousiou authored
- code cleanup: removal of unused signals and of the unused tstamps subtractions
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- 08 Oct, 2019 1 commit
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Evangelia Gousiou authored
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- 07 Oct, 2019 1 commit
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Evangelia Gousiou authored
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- 04 Oct, 2019 1 commit
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Evangelia Gousiou authored
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- 02 Oct, 2019 1 commit
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Evangelia Gousiou authored
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- 01 Oct, 2019 1 commit
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Evangelia Gousiou authored
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- 30 Sep, 2019 6 commits
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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- 29 Sep, 2019 3 commits
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Dimitris Lampridis authored
This reduces the required resources since we only use one set of adders for all channels (instead of one per). There is no issue with multiple timestamps arriving simultaneously, since the previous stages serialise the delivery of timestamps and this stage is fully pipelined, so it can process one timestamp per cycle.
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Dimitris Lampridis authored
[hdl] do not filter out falling edges in direct readout. This can be done if necessary by setting the relevant ACAM registers
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Dimitris Lampridis authored
Previous fix did not correctly account for when the most significant bit of a.frac was '1', as it would incorrectly consider it as a negative number. Also updated the header notes.
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- 28 Sep, 2019 1 commit
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Dimitris Lampridis authored
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- 27 Sep, 2019 5 commits
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Evangelia Gousiou authored
deleted scripts for ucf generation; now all the spec generic pinout comes with the spec submodule and are applied in the syn Manifest
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Evangelia Gousiou authored
updated submodules; added missing sim files
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 26 Sep, 2019 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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