Commit 29c1fdd2 authored by Evangelia Gousiou's avatar Evangelia Gousiou

wip testbench added infrastructure for dma test

parent 3fdaa92b
This diff is collapsed.
`define ADDR_DMA_CTRL 6'h0
`define ADDR_DMA_STAT 6'h4
`define ADDR_DMA_CSTART 6'h8
`define ADDR_DMA_HSTARTL 6'hc
`define ADDR_DMA_HSTARTH 6'h10
`define ADDR_DMA_LEN 6'h14
`define ADDR_DMA_NEXTL 6'h18
`define ADDR_DMA_NEXTH 6'h1c
`define ADDR_DMA_ATTRIB 6'h20
`define ADDR_VIC_CTL 8'h0
`define VIC_CTL_ENABLE_OFFSET 0
`define VIC_CTL_ENABLE 32'h00000001
`define VIC_CTL_POL_OFFSET 1
`define VIC_CTL_POL 32'h00000002
`define VIC_CTL_EMU_EDGE_OFFSET 2
`define VIC_CTL_EMU_EDGE 32'h00000004
`define VIC_CTL_EMU_LEN_OFFSET 3
`define VIC_CTL_EMU_LEN 32'h0007fff8
`define ADDR_VIC_RISR 8'h4
`define ADDR_VIC_IER 8'h8
`define ADDR_VIC_IDR 8'hc
`define ADDR_VIC_IMR 8'h10
`define ADDR_VIC_VAR 8'h14
`define ADDR_VIC_SWIR 8'h18
`define ADDR_VIC_EOIR 8'h1c
`define BASE_VIC_IVT_RAM 8'h80
`define SIZE_VIC_IVT_RAM 32'h20
......@@ -16,6 +16,7 @@ include_dirs = [
fetchto + "/general-cores/sim",
fetchto + "/general-cores/modules/wishbone/wb_lm32/src",
fetchto + "/wr-cores/sim",
fetchto + "/ddr3-sp6-core/hdl/sim/",
fetchto + "/general-cores/modules/wishbone/wb_spi",
]
......
......@@ -6,8 +6,8 @@ package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:ac0bebbb3c3f294441ec6282b18a38b27bd8d61b" & LF
& "commit:3fdaa92b28316925bd834b970aca201b4c4cd9cf" & LF
& "syntool:modelsim" & LF
& "syndate:2020-04-22, 22:57 CEST" & LF
& "syndate:2020-04-23, 00:03 CEST" & LF
& "synauth:Evangelia Gousiou" & LF;
end buildinfo_pkg;
import wishbone_pkg::*;
import tdc_core_pkg::*;
`timescale 1ns/1ps
`include "timestamp_fifo_regs.vh"
`include "tdc_eic_wb_regs.vh"
`include "tdc_core_csr_wb.vh"
`include "vic_wb.vh"
`include "dma_controller_wb.vh"
`include "gn4124_bfm.svh"
`include "simdrv_defs.svh"
`include "if_wb_master.svh"
`include "vhd_wishbone_master.svh"
`include "softpll_regs_ng.vh"
`include "gn4124_bfm.svh"
`include "acam_model.svh"
`define DMA_BASE 'h00c0
......@@ -134,12 +129,47 @@ class FmcTdcDriver;
function int poll();
$display("[Info] m_queues[0].size: %d", m_queues[0].size());
return (m_queues[0].size() > 2);
return (m_queues[0].size() > 10);
endfunction // poll
function fmc_tdc_timestamp_t get();
return m_queues[0].pop_front();
endfunction // get
// update DMA i/f
task automatic update_dma();
automatic uint32_t DMA_CH_base = `TDC_DMA_BASE + 'h100;
automatic uint32_t dma_pos, dma_len;
// read position?
//readl(`DMA_CH_base + `POS, dma_pos); position in DDR /////
$display("<%t> Start DMA, position in DDR: %.8x", $realtime, dma_pos);
// read length?
//readl(`DMA_CH_base + `POS, dma_len); position in DDR /////
$display("<%t> Start DMA, position in DDR: %.8x", $realtime, dma_len);
// DMA transfer
writel(`DMA_BASE + `ADDR_DMA_CSTART, dma_pos); // dma start addr
writel(`DMA_BASE + `ADDR_DMA_HSTARTL, 'h00001000); // host addr
writel(`DMA_BASE + `ADDR_DMA_HSTARTH, 'h00000000);
// length =
writel(`DMA_BASE + `ADDR_DMA_LEN, dma_len); // length
writel(`DMA_BASE + `ADDR_DMA_NEXTL, 'h00000000); // next
writel(`DMA_BASE + `ADDR_DMA_NEXTH, 'h00000000);
writel(`DMA_BASE + `ADDR_DMA_ATTRIB, 'h00000000); // attrib: pcie -> host
writel(`DMA_BASE + `ADDR_DMA_ATTRIB, 'h00000001); // xfer start
//wait (DUT.inst_spec_base.irqs[2]);
$display("<%t> END DMA", $realtime);
writel(`DMA_BASE + `ADDR_DMA_STAT, 'h04); // clear DMA IRQ
writel(`VIC_BASE + `ADDR_DMA_NEXTH, 'h0);
endtask // update_dma
endclass // FmcTdcDriver
......@@ -178,6 +208,14 @@ module main;
wire [4:1] tdc_stop_dis;
reg [8:1] tdc_stop = 0;
wire ddr_cas_n, ddr_ck_p, ddr_ck_n, ddr_cke;
wire [1:0] ddr_dm, ddr_dqs_p, ddr_dqs_n;
wire ddr_odt, ddr_ras_n, ddr_reset_n, ddr_we_n;
wire [15:0] ddr_dq;
wire [13:0] ddr_a;
wire [2:0] ddr_ba;
wire ddr_rzq;
// ACAM model instantiation
tdc_gpx_model
......@@ -250,8 +288,77 @@ module main;
.fmc0_tdc_start_from_fpga_o(tdc_start),
.fmc0_tdc_start_dis_o(tdc_start_dis),
.fmc0_tdc_stop_dis_o(tdc_stop_dis[1]),
`GENNUM_WIRE_SPEC_BTRAIN_REF(Host)
);
//`GENNUM_WIRE_SPEC_BTRAIN_REF(Host)
.gn_rst_n_i (Host.rst_n),
.gn_p2l_clk_n_i (Host.p2l_clk_n),
.gn_p2l_clk_p_i (Host.p2l_clk_p),
.gn_p2l_rdy_o (Host.p2l_rdy),
.gn_p2l_dframe_i (Host.p2l_dframe),
.gn_p2l_valid_i (Host.p2l_valid),
.gn_p2l_data_i (Host.p2l_data),
.gn_p_wr_req_i (Host.p_wr_req),
.gn_p_wr_rdy_o (Host.p_wr_rdy),
.gn_rx_error_o (Host.rx_error),
.gn_l2p_clk_n_o (Host.l2p_clk_n),
.gn_l2p_clk_p_o (Host.l2p_clk_p),
.gn_l2p_dframe_o (Host.l2p_dframe),
.gn_l2p_valid_o (Host.l2p_valid),
.gn_l2p_edb_o (Host.l2p_edb),
.gn_l2p_data_o (Host.l2p_data),
.gn_l2p_rdy_i (Host.l2p_rdy),
.gn_l_wr_rdy_i (Host.l_wr_rdy),
.gn_p_rd_d_rdy_i (Host.p_rd_d_rdy),
.gn_tx_error_i (Host.tx_error),
.gn_vc_rdy_i (Host.vc_rdy),
.gn_gpio_b (),
.ddr_a_o (ddr_a),
.ddr_ba_o (ddr_ba),
.ddr_cas_n_o (ddr_cas_n),
.ddr_ck_n_o (ddr_ck_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_cke_o (ddr_cke),
.ddr_dq_b (ddr_dq),
.ddr_ldm_o (ddr_dm[0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]),
.ddr_ldqs_p_b (ddr_dqs_p[0]),
.ddr_odt_o (ddr_odt),
.ddr_ras_n_o (ddr_ras_n),
.ddr_reset_n_o (ddr_reset_n),
.ddr_rzq_b (ddr_rzq),
.ddr_udm_o (ddr_dm[1]),
.ddr_udqs_n_b (ddr_dqs_n[1]),
.ddr_udqs_p_b (ddr_dqs_p[1]),
.ddr_we_n_o (ddr_we_n)
);
// DDR3 model instantiation
ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
cmp_ddr0
(
.rst_n (ddr_reset_n),
.ck (ddr_ck_p),
.ck_n (ddr_ck_n),
.cke (ddr_cke),
.cs_n (1'b0),
.ras_n (ddr_ras_n),
.cas_n (ddr_cas_n),
.we_n (ddr_we_n),
.dm_tdqs (ddr_dm),
.ba (ddr_ba),
.addr (ddr_a),
.dq (ddr_dq),
.dqs (ddr_dqs_p),
.dqs_n (ddr_dqs_n),
.tdqs_n (),
.odt (ddr_odt)
);
assign tdc_stop_dis[4] = tdc_stop_dis[1];
assign tdc_stop_dis[3] = tdc_stop_dis[1];
......
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