bugfix on fmc-id

3dab8e71 · Evangelia Gousiou · d50ff50a · 3dab8e71 · 3dab8e71 · 3dab8e71
Commit 3dab8e71 authored Mar 24, 2020 by Evangelia Gousiou
5 changed files
--- a/hdl/rtl/fmc_tdc_wrapper.vhd
+++ b/hdl/rtl/fmc_tdc_wrapper.vhd
@@ -94,20 +94,20 @@ entity fmc_tdc_wrapper is
  generic
    (
      -- reduces some timeouts to speed up simulation
-      g_simulation                  : boolean := false;
+      g_SIMULATION                  : boolean := false;
      -- implement direct TDC timestamp readout FIFO, used in the WR Node projects
-      g_with_direct_readout         : boolean := false;
+      g_WITH_DIRECT_READOUT         : boolean := false;
      -- Enable filtering based on pulse width. This will have the following effects:
      -- * Suppress theforwarding of negative slope timestamps.
      -- * Delay the forwarding of timestamps until after the falling edge timestamp.
      -- Once enabled, all pulses wider than 1 second or narrower than
      -- g_pulse_width_filter_min will be dropped.
-      g_pulse_width_filter          : boolean := true;
+      g_PULSE_WIDTH_FILTER          : boolean := true;
      -- In 8ns ticks.
-      g_pulse_width_filter_min      : natural := 12;
-      g_use_dma_readout             : boolean := false;
-      g_use_fifo_readout            : boolean := false;
-      g_use_fake_timestamps_for_sim : boolean := false
+      g_PULSE_WIDTH_FILTER_MIN      : natural := 12;
+      g_USE_DMA_READOUT             : boolean := false;
+      g_USE_FIFO_READOUT            : boolean := false;
+      g_USE_FAKE_TIMESTAMPS_FOR_SIM : boolean := false
      );
  port
    (

--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
@@ -94,7 +94,7 @@ entity reg_ctrl is
      local_utc_i : in std_logic_vector(g_width-1 downto 0);  -- local utc time

      -- Signals not used so far
-      core_status_i : in std_logic_vector(g_width-1 downto 0);  -- TDC core status word
+      core_status_i : in std_logic_vector(g_width-1 downto 0);  -- TDC core status word currently unused

      -- White Rabbit status
      wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);  -- 
@@ -521,6 +521,7 @@ begin
  with reg_adr_pipe0 select dat_out_comb3 <=
    -- regs written locally by the TDC core units
    local_utc_i          when c_CURRENT_UTC_ADR,
+    core_status_i        when c_CORE_STATUS_ADR,
    -- White Rabbit regs
    wrabbit_status_reg_i when c_WRABBIT_STATUS_ADR,
    wrabbit_ctrl_reg     when c_WRABBIT_CTRL_ADR,

--- a/hdl/rtl/tdc_core_pkg.vhd
+++ b/hdl/rtl/tdc_core_pkg.vhd
@@ -723,8 +723,13 @@ package tdc_core_pkg is

  component fmc_tdc_wrapper is
    generic (
-      g_simulation          : boolean := false;
-      g_with_direct_readout : boolean := false);
+      g_SIMULATION                  : boolean := false;
+      g_WITH_DIRECT_READOUT         : boolean := false;
+      g_PULSE_WIDTH_FILTER          : boolean := true;
+      g_PULSE_WIDTH_FILTER_MIN      : natural := 12;
+      g_USE_DMA_READOUT             : boolean := false;
+      g_USE_FIFO_READOUT            : boolean := false;
+      g_USE_FAKE_TIMESTAMPS_FOR_SIM : boolean := false);
    port (
      clk_sys_i            : in    std_logic;
      rst_sys_n_i          : in    std_logic;
@@ -759,12 +764,8 @@ package tdc_core_pkg is
      term_en_3_o          : out   std_logic;
      term_en_4_o          : out   std_logic;
      term_en_5_o          : out   std_logic;
-      tdc_led_status_o     : out   std_logic;
-      tdc_led_trig1_o      : out   std_logic;
-      tdc_led_trig2_o      : out   std_logic;
-      tdc_led_trig3_o      : out   std_logic;
-      tdc_led_trig4_o      : out   std_logic;
-      tdc_led_trig5_o      : out   std_logic;
+      tdc_led_stat_o       : out   std_logic;
+      tdc_led_trig_o      : out   std_logic_vector(4 downto 0);
      mezz_scl_o           : out std_logic;
      mezz_sda_o           : out std_logic;
      mezz_scl_i           : in std_logic;

--- a/hdl/rtl/wbgen/reg_ctrl_wb.wb
+++ b/hdl/rtl/wbgen/reg_ctrl_wb.wb
--- a/hdl/syn/spec/wr_spec_tdc.xise
+++ b/hdl/syn/spec/wr_spec_tdc.xise