Commit ffbd8dd8 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

testbench/spec: Tom's work on DMA

- initialize TDC DMA Engine (buffer controller)
- reset the SPEC/DDR contoller prior to operation (still wip)
- feed the design with fake timestamps bypassing ACAM, let's debug one thing at a time.

This is a WIP commit, I see the core writing the timestamps to the DDR, but the Gennum-side DMA as well as double-buffering of the DDR timestamps is yet to be implemented.

Note: I've never managed to simulate DMA with the crappy Gennum VHDL model. I guess we need to fix it or write a new one..
parent 9c68bf4e
......@@ -6,8 +6,8 @@ package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:29c1fdd2e474c7bdb52e11db26e94b502814290e" & LF
& "commit:745e912cee76d4ee9e8c3fded1c9ee9b5e694cdd" & LF
& "syntool:modelsim" & LF
& "syndate:2020-04-24, 17:39 CEST" & LF
& "synauth:Evangelia Gousiou" & LF;
& "syndate:2020-04-24, 22:37 CEST" & LF
& "synauth:Tomasz Wlostowski" & LF;
end buildinfo_pkg;
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