testbench/spec: Tom's work on DMA
- initialize TDC DMA Engine (buffer controller) - reset the SPEC/DDR contoller prior to operation (still wip) - feed the design with fake timestamps bypassing ACAM, let's debug one thing at a time. This is a WIP commit, I see the core writing the timestamps to the DDR, but the Gennum-side DMA as well as double-buffering of the DDR timestamps is yet to be implemented. Note: I've never managed to simulate DMA with the crappy Gennum VHDL model. I guess we need to fix it or write a new one..
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