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FMC TDC 1ns 5cha - Gateware
Commit b5bc6601 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] use the same timestamp data path for fifo_readout, dma_readout and direct_readout

parent 6ed2a256
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Showing with 51 additions and 115 deletions
hdl/rtl/fmc_tdc_core.vhd
View file @ b5bc6601
......@@ -226,10 +226,6 @@ entity fmc_tdc_core is
timestamp_valid_o : out std_logic_vector(4 downto 0);
timestamp_ready_i : in std_logic_vector(4 downto 0);
-- direct interface, for compatibility with LIST/WRTD
direct_timestamp_o : out std_logic_vector(127 downto 0);
direct_timestamp_valid_o : out std_logic;
channel_enable_o : out std_logic_vector(4 downto 0);
irq_threshold_o : out std_logic_vector(9 downto 0);
irq_timeout_o : out std_logic_vector(9 downto 0)
......@@ -560,9 +556,7 @@ begin
ts_ready_i => final_timestamp_ready,
ts_offset_i => ts_offset_i,
reset_seq_i => reset_seq_i,
raw_enable_i => raw_enable_i,
direct_timestamp_o => direct_timestamp_o,
direct_timestamp_valid_o => direct_timestamp_valid_o
raw_enable_i => raw_enable_i
);
......
hdl/rtl/fmc_tdc_direct_readout.vhd
View file @ b5bc6601
......@@ -11,14 +11,11 @@ use work.dr_wbgen2_pkg.all;
entity fmc_tdc_direct_readout is
port
(
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
direct_timestamp_i : in std_logic_vector(127 downto 0);
direct_timestamp_wr_i : in std_logic;
timestamp_i : in t_tdc_timestamp_array(4 downto 0);
timestamp_valid_i : in std_logic_vector(4 downto 0);
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out
......@@ -29,24 +26,6 @@ end entity;
architecture rtl of fmc_tdc_direct_readout is
component fmc_tdc_direct_readout_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_tdc_i : in std_logic;
regs_i : in t_dr_in_registers;
regs_o : out t_dr_out_registers);
end component fmc_tdc_direct_readout_wb_slave;
constant c_num_channels : integer := 5;
type t_channel_state is record
......@@ -65,24 +44,33 @@ architecture rtl of fmc_tdc_direct_readout is
signal regs_out : t_dr_out_registers;
signal regs_in : t_dr_in_registers;
signal ts_cycles : std_logic_vector(31 downto 0);
signal ts_seconds : std_logic_vector(31 downto 0);
signal ts_bins : std_logic_vector(17 downto 0);
signal ts_edge : std_logic;
signal ts_channel : std_logic_vector(2 downto 0);
signal direct_slave_out: t_wishbone_slave_out;
begin
signal channel_select : integer := 0;
ts_channel <= direct_timestamp_i(98 downto 96);
ts_edge <= direct_timestamp_i(99);
ts_seconds <= direct_timestamp_i(31 downto 0);
ts_cycles <= direct_timestamp_i(63 downto 32);
ts_bins <= direct_timestamp_i(81 downto 64);
begin
U_WB_Slave : fmc_tdc_direct_readout_wb_slave
p_channel_select: process (timestamp_valid_i) is
begin
case timestamp_valid_i is
when "00001" => channel_select <= 0;
when "00010" => channel_select <= 1;
when "00100" => channel_select <= 2;
when "01000" => channel_select <= 3;
when "10000" => channel_select <= 4;
when others => channel_select <= 0;
end case;
end process p_channel_select;
regs_in.fifo_cycles_i <= timestamp_i(channel_select).coarse;
regs_in.fifo_edge_i <= timestamp_i(channel_select).slope;
regs_in.fifo_seconds_i <= timestamp_i(channel_select).tai;
regs_in.fifo_channel_i <= std_logic_vector(to_unsigned(channel_select, 4));
regs_in.fifo_bins_i <= "000000" & timestamp_i(channel_select).frac;
regs_in.fifo_wr_req_i <= f_to_std_logic(fifo_wr(channel_select) = '1' and
regs_out.fifo_wr_full_o = '0');
U_WB_Slave : entity work.fmc_tdc_direct_readout_wb_slave
port map (
rst_n_i => rst_sys_n_i,
clk_sys_i => clk_sys_i,
......@@ -95,7 +83,7 @@ begin
wb_we_i => direct_slave_i.we,
wb_ack_o => direct_slave_out.ack,
wb_stall_o => direct_slave_out.stall,
clk_tdc_i => clk_tdc_i,
clk_tdc_i => clk_sys_i,
regs_i => regs_in,
regs_o => regs_out);
......@@ -104,26 +92,18 @@ begin
direct_slave_o <= direct_slave_out;
regs_in.fifo_cycles_i <= ts_cycles;
regs_in.fifo_edge_i <= '1';
regs_in.fifo_seconds_i <= ts_seconds;
regs_in.fifo_channel_i <= '0'&ts_channel;
regs_in.fifo_bins_i <= ts_bins;
regs_in.fifo_wr_req_i <= f_to_std_logic(fifo_wr /= (fifo_wr'range => '0')
and regs_out.fifo_wr_full_o = '0');
gen_channels : for i in 0 to c_num_channels-1 generate
c(i).enable <= regs_out.chan_enable_o(i);
fifo_wr(i) <= f_to_std_logic(unsigned(ts_channel) = i
and ts_edge = '1'
and direct_timestamp_wr_i = '1'
and c(i).ready = '1');
fifo_wr(i) <= f_to_std_logic(timestamp_i(i).slope = '1'and
timestamp_valid_i(i) = '1'and
c(i).ready = '1');
p_dead_time : process (clk_tdc_i)
p_dead_time : process (clk_sys_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_n_i = '0' or c(i).enable = '0' then
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or c(i).enable = '0' then
c(i).timeout <= (others => '0');
c(i).ready <= '0';
else
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ b5bc6601
......@@ -194,8 +194,9 @@ entity fmc_tdc_mezzanine is
i2c_sda_i : in std_logic;
-- 1-Wire interface
onewire_b : inout std_logic;
direct_timestamp_o : out std_logic_vector(127 downto 0);
direct_timestamp_valid_o : out std_logic;
timestamp_o : out t_tdc_timestamp_array(4 downto 0);
timestamp_valid_o : out std_logic_vector(4 downto 0);
sim_timestamp_i : in t_tdc_timestamp := c_dummy_timestamp;
sim_timestamp_valid_i : in std_logic := '0';
......@@ -400,9 +401,6 @@ begin
ts_offset_i => ts_offset,
reset_seq_i => reset_seq,
direct_timestamp_valid_o => direct_timestamp_valid_o,
direct_timestamp_o => direct_timestamp_o,
irq_threshold_o => irq_threshold,
irq_timeout_o => irq_timeout,
channel_enable_o => channel_enable
......@@ -435,8 +433,8 @@ begin
tdc_timestamp_ready <= timestamp_ready;
end generate gen_use_real_timestamps;
timestamp_o <= timestamp;
timestamp_valid_o <= timestamp_valid;
gen_enable_fifo_readout : if g_use_fifo_readout generate
gen_fifos : for i in 0 to 4 generate
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ b5bc6601
......@@ -248,18 +248,6 @@ end fmc_tdc_wrapper;
--=================================================================================================
architecture rtl of fmc_tdc_wrapper is
component fmc_tdc_direct_readout is
port (
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
direct_timestamp_i : in std_logic_vector(127 downto 0);
direct_timestamp_wr_i : in std_logic;
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out);
end component fmc_tdc_direct_readout;
-- WRabbit clocks
signal clk_125m_mezz : std_logic;
signal rst_125m_mezz_n, rst_125m_mezz : std_logic;
......@@ -276,8 +264,8 @@ architecture rtl of fmc_tdc_wrapper is
signal tdc_scl_out, tdc_scl_oen, tdc_sda_out, tdc_sda_oen : std_logic;
signal direct_timestamp : std_logic_vector(127 downto 0);
signal direct_timestamp_wr : std_logic;
signal timestamp : t_tdc_timestamp_array(4 downto 0);
signal timestamp_valid : std_logic_vector(4 downto 0);
constant c_cnx_slave_ports : integer := 2;
constant c_cnx_master_ports : integer := 2;
......@@ -328,16 +316,14 @@ begin
master_i => cnx_master_in,
master_o => cnx_master_out);
cmp_direct_readout : fmc_tdc_direct_readout
cmp_direct_readout : entity work.fmc_tdc_direct_readout
port map (
clk_tdc_i => clk_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
direct_timestamp_i => direct_timestamp,
direct_timestamp_wr_i => direct_timestamp_wr,
direct_slave_i => cnx_master_out(c_slave_direct),
direct_slave_o => cnx_master_in(c_slave_direct));
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
timestamp_i => timestamp,
timestamp_valid_i => timestamp_valid,
direct_slave_i => cnx_master_out(c_slave_direct),
direct_slave_o => cnx_master_in(c_slave_direct));
end generate gen_with_direct_readout;
......@@ -489,8 +475,9 @@ begin
i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine
onewire_b => mezz_one_wire_b,
direct_timestamp_o => direct_timestamp,
direct_timestamp_valid_o => direct_timestamp_wr,
timestamp_o => timestamp,
timestamp_valid_o => timestamp_valid,
sim_timestamp_ready_o => sim_timestamp_ready_o,
sim_timestamp_valid_i => sim_timestamp_valid_i,
......
hdl/rtl/timestamp_convert_filter.vhd
View file @ b5bc6601
......@@ -35,13 +35,8 @@ entity timestamp_convert_filter is
ts_offset_i : in t_tdc_timestamp_array(4 downto 0);
ts_o : out t_tdc_timestamp_array(4 downto 0);
ts_valid_o : buffer std_logic_vector(4 downto 0);
ts_ready_i : in std_logic_vector(4 downto 0);
direct_timestamp_o : out std_logic_vector(127 downto 0);
direct_timestamp_valid_o : out std_logic
ts_ready_i : in std_logic_vector(4 downto 0)
);
end timestamp_convert_filter;
architecture rtl of timestamp_convert_filter is
......@@ -197,24 +192,6 @@ architecture rtl of timestamp_convert_filter is
s3_ts.channel <= s3_channel;
s3_ts.meta <= s3_meta;
p_direct_output : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' then
direct_timestamp_valid_o <= '0';
else
direct_timestamp_o(31 downto 0) <= s3_ts.tai;
direct_timestamp_o(63 downto 32) <= s3_ts.coarse;
direct_timestamp_o(95 downto 64) <= x"00000" & s3_ts.frac;
direct_timestamp_o(96 + 2 downto 96) <= s3_ts.channel;
direct_timestamp_o(96 + 3) <= s3_ts.slope;
direct_timestamp_o(127 downto 100) <= (others => '0');
direct_timestamp_valid_o <= s3_valid;
end if;
end if;
end process;
gen_channels : for i in 0 to 4 generate
gen_with_pwidth_filter : if g_PULSE_WIDTH_FILTER generate
......
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