testbench: add register headers for the SPEC CSR & TDC DMA Buffer

9c68bf4e · Tomasz Wlostowski · b0abfca5 · 9c68bf4e · 9c68bf4e
Commit 9c68bf4e authored Apr 24, 2020 by Tomasz Wlostowski
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spec_base_regs.vh hdl/testbench/include/regs/spec_base_regs.vh +33 -0

tdc_buffer_control_regs.vh hdl/testbench/include/regs/tdc_buffer_control_regs.vh +26 -0

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--- a/hdl/testbench/include/regs/spec_base_regs.vh
+++ b/hdl/testbench/include/regs/spec_base_regs.vh
+`define SPEC_BASE_REGS_SIZE 8192
+`define ADDR_SPEC_BASE_REGS_METADATA 'h0
+`define SPEC_BASE_REGS_METADATA_SIZE 64
+`define ADDR_SPEC_BASE_REGS_CSR 'h40
+`define SPEC_BASE_REGS_CSR_SIZE 32
+`define ADDR_SPEC_BASE_REGS_CSR_APP_OFFSET 'h40
+`define ADDR_SPEC_BASE_REGS_CSR_RESETS 'h44
+`define SPEC_BASE_REGS_CSR_RESETS_GLOBAL_OFFSET 0
+`define SPEC_BASE_REGS_CSR_RESETS_GLOBAL 'h1
+`define SPEC_BASE_REGS_CSR_RESETS_APPL_OFFSET 1
+`define SPEC_BASE_REGS_CSR_RESETS_APPL 'h2
+`define ADDR_SPEC_BASE_REGS_CSR_FMC_PRESENCE 'h48
+`define ADDR_SPEC_BASE_REGS_CSR_GN4124_STATUS 'h4c
+`define ADDR_SPEC_BASE_REGS_CSR_DDR_STATUS 'h50
+`define SPEC_BASE_REGS_CSR_DDR_STATUS_CALIB_DONE_OFFSET 0
+`define SPEC_BASE_REGS_CSR_DDR_STATUS_CALIB_DONE 'h1
+`define ADDR_SPEC_BASE_REGS_CSR_PCB_REV 'h54
+`define SPEC_BASE_REGS_CSR_PCB_REV_REV_OFFSET 0
+`define SPEC_BASE_REGS_CSR_PCB_REV_REV 'hf
+`define ADDR_SPEC_BASE_REGS_THERM_ID 'h70
+`define SPEC_BASE_REGS_THERM_ID_SIZE 16
+`define ADDR_SPEC_BASE_REGS_FMC_I2C 'h80
+`define SPEC_BASE_REGS_FMC_I2C_SIZE 32
+`define ADDR_SPEC_BASE_REGS_FLASH_SPI 'ha0
+`define SPEC_BASE_REGS_FLASH_SPI_SIZE 32
+`define ADDR_SPEC_BASE_REGS_DMA 'hc0
+`define SPEC_BASE_REGS_DMA_SIZE 64
+`define ADDR_SPEC_BASE_REGS_VIC 'h100
+`define SPEC_BASE_REGS_VIC_SIZE 256
+`define ADDR_SPEC_BASE_REGS_BUILDINFO 'h200
+`define SPEC_BASE_REGS_BUILDINFO_SIZE 256
+`define ADDR_SPEC_BASE_REGS_WRC_REGS 'h1000
+`define SPEC_BASE_REGS_WRC_REGS_SIZE 4096
--- a/hdl/testbench/include/regs/tdc_buffer_control_regs.vh
+++ b/hdl/testbench/include/regs/tdc_buffer_control_regs.vh
+`define ADDR_TDC_BUF_CSR               5'h0
+`define TDC_BUF_CSR_ENABLE_OFFSET 0
+`define TDC_BUF_CSR_ENABLE 32'h00000001
+`define TDC_BUF_CSR_IRQ_TIMEOUT_OFFSET 1
+`define TDC_BUF_CSR_IRQ_TIMEOUT 32'h000007fe
+`define TDC_BUF_CSR_BURST_SIZE_OFFSET 11
+`define TDC_BUF_CSR_BURST_SIZE 32'h001ff800
+`define TDC_BUF_CSR_SWITCH_BUFFERS_OFFSET 21
+`define TDC_BUF_CSR_SWITCH_BUFFERS 32'h00200000
+`define TDC_BUF_CSR_DONE_OFFSET 22
+`define TDC_BUF_CSR_DONE 32'h00400000
+`define TDC_BUF_CSR_OVERFLOW_OFFSET 23
+`define TDC_BUF_CSR_OVERFLOW 32'h00800000
+`define ADDR_TDC_BUF_CUR_BASE          5'h4
+`define ADDR_TDC_BUF_CUR_COUNT         5'h8
+`define ADDR_TDC_BUF_CUR_SIZE          5'hc
+`define TDC_BUF_CUR_SIZE_SIZE_OFFSET 0
+`define TDC_BUF_CUR_SIZE_SIZE 32'h3fffffff
+`define TDC_BUF_CUR_SIZE_VALID_OFFSET 30
+`define TDC_BUF_CUR_SIZE_VALID 32'h40000000
+`define ADDR_TDC_BUF_NEXT_BASE         5'h10
+`define ADDR_TDC_BUF_NEXT_SIZE         5'h14
+`define TDC_BUF_NEXT_SIZE_SIZE_OFFSET 0
+`define TDC_BUF_NEXT_SIZE_SIZE 32'h3fffffff
+`define TDC_BUF_NEXT_SIZE_VALID_OFFSET 30
+`define TDC_BUF_NEXT_SIZE_VALID 32'h40000000