wr_spec_tdc: expose sim_timestamp interface to feed fake timestamps to the core…

wr_spec_tdc: expose sim_timestamp interface to feed fake timestamps to the core without modelling the ACAM chip

wr_spec_tdc: expose sim_timestamp interface to feed fake timestamps to the core…
wr_spec_tdc: expose sim_timestamp interface to feed fake timestamps to the core without modelling the ACAM chip
b0abfca5 · Tomasz Wlostowski · 2d7e81e1 · b0abfca5
Commit b0abfca5 authored Apr 24, 2020 by Tomasz Wlostowski
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wr_spec_tdc.vhd hdl/top/spec/wr_spec_tdc.vhd +7 -1

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--- a/hdl/top/spec/wr_spec_tdc.vhd
+++ b/hdl/top/spec/wr_spec_tdc.vhd
@@ -705,7 +705,13 @@ begin
      dma_wb_o             => fmc0_wb_ddr_out,

      irq_o                => irq_vector(0),
-      clk_125m_tdc_o       => tdc0_clk_125m);
+      clk_125m_tdc_o       => tdc0_clk_125m,
+
+      sim_timestamp_i       => sim_ts,
+      sim_timestamp_valid_i => sim_ts_valid,
+      sim_timestamp_ready_o => sim_ts_ready
+
+      );

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  fmc0_wb_ddr_in.err <= '0';