[hdl] stop using an async FIFO for direct readout, timestamps are already in the sys clock domain.

d5ef17f8 · Dimitris Lampridis · b5bc6601 · d5ef17f8 · d5ef17f8 · d5ef17f8
Commit d5ef17f8 authored Sep 26, 2019 by Dimitris Lampridis
4 changed files
--- a/hdl/rtl/fmc_tdc_direct_readout.vhd
+++ b/hdl/rtl/fmc_tdc_direct_readout.vhd
@@ -83,7 +83,6 @@ begin
      wb_we_i    => direct_slave_i.we,
      wb_ack_o   => direct_slave_out.ack,
      wb_stall_o => direct_slave_out.stall,
-      clk_tdc_i  => clk_sys_i,
      regs_i     => regs_in,
      regs_o     => regs_out);


--- a/hdl/rtl/fmc_tdc_direct_readout_slave.vhd
+++ b/hdl/rtl/fmc_tdc_direct_readout_slave.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fmc_tdc_direct_readout_slave.vhd
 -- Author         : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb
-- Created        : Thu May 22 14:05:35 2014
+-- Created        : Thu Sep 26 16:03:31 2019
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb
@@ -30,8 +30,9 @@ entity fmc_tdc_direct_readout_wb_slave is
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
+    wb_err_o                                 : out    std_logic;
+    wb_rty_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-    clk_tdc_i                                : in     std_logic;
    regs_i                                   : in     t_dr_in_registers;
    regs_o                                   : out    t_dr_out_registers
  );
@@ -61,13 +62,8 @@ signal allones                                  : std_logic_vector(31 downto 0);
 signal allzeros                                 : std_logic_vector(31 downto 0);

 begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
  wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
  process (clk_sys_i, rst_n_i)
@@ -223,7 +219,7 @@ begin
  dr_fifo_in_int(82) <= regs_i.fifo_edge_i;
  dr_fifo_in_int(86 downto 83) <= regs_i.fifo_channel_i;
  dr_fifo_rst_n <= rst_n_i;
-  dr_fifo_INST : wbgen2_fifo_async
+  dr_fifo_INST : wbgen2_fifo_sync
    generic map (
      g_size               => 256,
      g_width              => 87,
@@ -239,8 +235,7 @@ begin
      rd_usedw_o           => dr_fifo_usedw_int,
      rd_req_i             => dr_fifo_rdreq_int,
      rst_n_i              => dr_fifo_rst_n,
-      wr_clk_i             => clk_tdc_i,
-      rd_clk_i             => clk_sys_i,
+      clk_i                => clk_sys_i,
      wr_data_i            => dr_fifo_in_int,
      rd_data_o            => dr_fifo_out_int
    );
@@ -264,6 +259,8 @@ begin
 -- extra code for reg/fifo/mem: FIFO 'Readout FIFO' data output register 2
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+  wb_err_o <= '0';
+  wb_rty_o <= '0';
 -- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
 end syn;
--- a/hdl/rtl/fmc_tdc_direct_readout_slave_pkg.vhd
+++ b/hdl/rtl/fmc_tdc_direct_readout_slave_pkg.vhd
@@ -2,11 +2,11 @@
 -- Title          : Wishbone slave core for TDC Direct Readout WB Slave
 ---------------------------------------------------------------------------------------
 -- File           : fmc_tdc_direct_readout_slave_pkg.vhd
-- Author         : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb
-- Created        : Thu May 22 14:05:35 2014
+-- Author         : auto-generated by wbgen2 from wbgen/fmc_tdc_direct_readout_slave.wb
+-- Created        : Thu Sep 26 16:03:31 2019
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/fmc_tdc_direct_readout_slave.wb
 -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
 ---------------------------------------------------------------------------------------

@@ -73,10 +73,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
 variable tmp: std_logic_vector(x'length-1 downto 0);
 begin
 for i in 0 to x'length-1 loop
-if(x(i) = 'X' or x(i) = 'U') then
-tmp(i):= '0';
+if(x(i) = '1') then
+tmp(i):= '1';
 else
-tmp(i):=x(i);
+tmp(i):= '0';
 end if; 
 end loop; 
 return tmp;

--- a/hdl/rtl/wbgen/fmc_tdc_direct_readout_slave.wb
+++ b/hdl/rtl/wbgen/fmc_tdc_direct_readout_slave.wb
@@ -13,8 +13,6 @@ peripheral
      flags_bus = {FIFO_EMPTY, FIFO_FULL, FIFO_COUNT, FIFO_RESET};
      flags_dev = {FIFO_EMPTY, FIFO_FULL, FIFO_COUNT, FIFO_RESET};

-      clock = "clk_tdc_i";
-
      field {
         name = "Seconds";
 	 prefix = "SECONDS";
@@ -53,7 +51,6 @@ peripheral
   reg {
      name = "Channel Enable Register";
      prefix = "CHAN_ENABLE";
-      clock = "clk_tdc_i";
      field {
         name = "Channel enable";
         size = 5;
@@ -66,8 +63,6 @@ peripheral
   reg {
      name = "Dead Time Register";
      prefix = "DEAD_TIME";
-      clock = "clk_tdc_i";
-
      field {
         name = "Dead time (8ns ticks)";
         size = 24;
@@ -76,4 +71,4 @@ peripheral
 	 access_dev = READ_ONLY;
      };
   };
-};
\ No newline at end of file
+};