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FMC TDC 1ns 5cha - Gateware
Commit d50ff50a authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- correction of onewire sdb declaration for a reading of all the regs 

- code cleanup: removal of unused signals and of the unused tstamps subtractions
parent ca5ace53
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Showing with 1171 additions and 1247 deletions
hdl/rtl/Manifest.py
View file @ d50ff50a
files = [
"tdc_core_pkg.vhd",
"reg_ctrl_pkg.vhd",
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"carrier_info.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
......
hdl/rtl/data_engine.vhd
View file @ d50ff50a
......@@ -60,6 +60,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.reg_ctrl_pkg.all; -- reg map
use work.gencores_pkg.all;
......@@ -80,7 +81,7 @@ entity data_engine is
activate_acq_p_i : in std_logic; -- activates tstamps aquisition
deactivate_acq_p_i : in std_logic; -- for configuration readings/ writings
acam_wr_config_p_i : in std_logic; -- enables writing acam_config_i values to ACAM regs 0-7, 11, 12, 14
acam_rst_p_i : in std_logic; -- enables writing c_RESET_WORD to ACAM reg 4
acam_rst_p_i : in std_logic; -- enables writing reset_word to ACAM reg 4
acam_rdbk_config_p_i : in std_logic; -- enables reading of ACAM regs 0-7, 11, 12, 14
acam_rdbk_status_p_i : in std_logic; -- enables reading of ACAM reg 12
acam_rdbk_ififo1_p_i : in std_logic; -- enables reading of ACAM reg 8
......
hdl/rtl/fmc_tdc_core.vhd
View file @ d50ff50a
......@@ -190,9 +190,10 @@ entity fmc_tdc_core is
reset_seq_i : in std_logic_vector(4 downto 0);
raw_enable_i : in std_logic_vector(4 downto 0);
timestamp_o : out t_tdc_timestamp_array(4 downto 0);
timestamp_valid_o : out std_logic_vector(4 downto 0);
timestamp_ready_i : in std_logic_vector(4 downto 0);
timestamp_o : out t_tdc_timestamp_array(4 downto 0);
timestamp_valid_o : out std_logic_vector(4 downto 0);
timestamp_valid_p_o : out std_logic_vector(4 downto 0);
timestamp_ready_i : in std_logic_vector(4 downto 0);
channel_enable_o : out std_logic_vector(4 downto 0);
irq_threshold_o : out std_logic_vector(9 downto 0);
......@@ -222,7 +223,7 @@ architecture rtl of fmc_tdc_core is
signal read_ififo2, read_start01, reset_acam, load_utc : std_logic;
signal roll_over_incr_recent : std_logic;
signal deactivate_chan : std_logic_vector(4 downto 0);
signal pulse_delay, window_delay, clk_period : std_logic_vector(g_width-1 downto 0);
signal clk_period : std_logic_vector(g_width-1 downto 0);
signal starting_utc, acam_inputs_en : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1, acam_ififo2, acam_start01 : std_logic_vector(g_width-1 downto 0);
signal irq_tstamp_threshold, irq_time_threshold : std_logic_vector(g_width-1 downto 0);
......@@ -305,23 +306,21 @@ begin
acam_ififo2_i => acam_ififo2,
acam_start01_i => acam_start01,
local_utc_i => utc,
irq_code_i => x"00000000",
core_status_i => core_status,
wrabbit_status_reg_i => wrabbit_status_reg_i,
wrabbit_ctrl_reg_o => wrabbit_ctrl_reg,
acam_config_o => acam_config,
starting_utc_o => starting_utc,
acam_inputs_en_o => acam_inputs_en,
start_phase_o => window_delay,
irq_tstamp_threshold_o => irq_tstamp_threshold,
irq_time_threshold_o => irq_time_threshold,
send_dac_word_p_o => send_dac_word_p_o,
dac_word_o => dac_word_o,
one_hz_phase_o => pulse_delay,
gen_fake_ts_period_o => gen_fake_ts_period,
gen_fake_ts_enable_o => gen_fake_ts_enable,
gen_fake_ts_channel_o => gen_fake_ts_channel,
int_flag_delay_o => int_flag_delay
-----------------------------------------------------------
gen_fake_ts_period_o => gen_fake_ts_period, -- for debug
gen_fake_ts_enable_o => gen_fake_ts_enable, -- for debug
gen_fake_ts_channel_o => gen_fake_ts_channel, -- for debug
int_flag_delay_o => int_flag_delay -- for debug
);
process(clk_tdc_i)
......@@ -372,7 +371,6 @@ begin
clk_i => clk_tdc_i,
clk_period_i => clk_period,
load_utc_p_i => load_utc,
pulse_delay_i => pulse_delay,
rst_i => rst_tdc,
starting_utc_i => starting_utc,
local_utc_o => local_utc,
......@@ -430,8 +428,8 @@ begin
start_retrigger_block : entity work.start_retrig_ctrl
port map
(
int_flag_delay_i => int_flag_delay,
int_flag_i => int_flag_i,
int_flag_delay_i => int_flag_delay, -- for debug
int_flag_i => int_flag_i,
clk_i => clk_tdc_i,
utc_p_i => utc_p,
rst_i => rst_tdc,
......@@ -510,7 +508,7 @@ begin
---------------------------------------------------------------------------------------------------
-- TSTAMP FINAL FORMAT --
-- ADDITION OF OFFSETS (EX.CALIBRATION) --
-- ADDITION OF FIXED OFFSETS (PER CHANNEL CALIBRATION) --
-- FILTERING BY PULSE WIDTH --
-- SUBTRACTIONS BETWEEN CHANNELS --
---------------------------------------------------------------------------------------------------
......@@ -523,12 +521,12 @@ begin
rst_tdc_n_i => rst_tdc_n_i,
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
enable_i => channel_enable_sys,
ts_i => raw_timestamp,
ts_valid_i => raw_timestamp_valid,
ts_o => final_timestamp,
ts_valid_o => final_timestamp_valid,
ts_valid_p_o => timestamp_valid_p_o,
ts_ready_i => final_timestamp_ready,
ts_offset_i => ts_offset_i,
reset_seq_i => reset_seq_i,
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ d50ff50a
......@@ -225,11 +225,11 @@ architecture rtl of fmc_tdc_mezzanine is
-- WISHBONE crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
(0 => f_sdb_embed_device(c_TDC_ONEWIRE_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00002000"),
2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00003000"),
3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00004000"),
4 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005000"),
(c_WB_SLAVE_TDC_ONEWIRE => f_sdb_embed_device(c_TDC_ONEWIRE_SDB_DEVICE, x"00001000"),
c_WB_SLAVE_TDC_CORE_CONFIG => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00002000"),
c_WB_SLAVE_TDC_EIC => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00003000"),
c_WB_SLAVE_TDC_I2C => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00004000"),
c_WB_SLAVE_TDC_CHANNEL0 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005000"),
5 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005100"),
6 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005200"),
7 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005300"),
......@@ -268,6 +268,7 @@ architecture rtl of fmc_tdc_mezzanine is
signal timestamp_valid, timestamp_ready, timestamp_stb : std_logic_vector(4 downto 0);
signal tdc_timestamp : t_tdc_timestamp_array(4 downto 0);
signal tdc_timestamp_valid, tdc_timestamp_ready : std_logic_vector(4 downto 0);
signal tdc_timestamp_valid_p : std_logic_vector(4 downto 0);
signal channel_enable : std_logic_vector(4 downto 0);
signal irq_threshold, irq_timeout : std_logic_vector(9 downto 0);
signal tick_1ms : std_logic;
......@@ -374,12 +375,13 @@ begin
cfg_slave_i => f_wb_shift_address_word(cnx_master_out(c_WB_SLAVE_TDC_CORE_CONFIG)),
cfg_slave_o => cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG),
timestamp_o => tdc_timestamp,
timestamp_valid_o => tdc_timestamp_valid,
timestamp_ready_i => tdc_timestamp_ready,
timestamp_o => tdc_timestamp,
timestamp_valid_o => tdc_timestamp_valid,
timestamp_valid_p_o => tdc_timestamp_valid_p,
timestamp_ready_i => tdc_timestamp_ready,
raw_enable_i => raw_enable,
ts_offset_i => ts_offset, -- to be used by the direct readout
ts_offset_i => ts_offset,
reset_seq_i => reset_seq,
fmc_id_i => fmc_id_i,
......@@ -409,11 +411,11 @@ begin
irq_timeout_i => irq_timeout,
timestamp_i => timestamp(i),
timestamp_valid_i => timestamp_stb(i),
ts_offset_o => ts_offset(i),
ts_offset_o => ts_offset(i), -- to be used by the direct readout
reset_seq_o => reset_seq(i),
raw_enable_o => raw_enable(i));
timestamp_stb(i) <= timestamp_valid(i) and timestamp_ready(i);
timestamp_stb(i) <= tdc_timestamp_valid_p(i);
end generate gen_fifos;
---------------------------------------------------------------------------------------------------
......@@ -516,6 +518,20 @@ begin
-- TDC Mezzanine Board UniqueID&Thermometer OneWire --
---------------------------------------------------------------------------------------------------
U_OnewireIF : gc_ds182x_readout
generic map (
g_CLOCK_FREQ_KHZ => 62500,
g_USE_INTERNAL_PPS => true)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
pps_p_i => '0',
onewire_b => onewire_b,
id_o(63 downto 32) => regs_ow_in.tdc_ow_id_h_i,
id_o(31 downto 0) => regs_ow_in.tdc_ow_id_l_i,
temper_o => regs_ow_in.tdc_ow_temp_i,
id_read_o => regs_ow_in.tdc_ow_csr_valid_i);
U_Onewire : entity work.tdc_onewire_wb
port map (
rst_n_i => rst_sys_n_i,
......@@ -525,7 +541,7 @@ begin
regs_i => regs_ow_in,
regs_o => regs_ow_out);
gen_enable_eic : if g_use_fifo_readout or g_use_dma_readout generate
---------------------------------------------------------------------------------------------------
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
......@@ -534,6 +550,8 @@ begin
-- 0 -> number of accumulated timestamps reached threshold
-- 1 -> number of seconds passed reached threshold and number of accumulated tstamps > 0
-- 2 -> ACAM error
gen_enable_eic : if g_use_fifo_readout or g_use_dma_readout generate
cmp_tdc_eic : entity work.tdc_eic
port map
(clk_sys_i => clk_sys_i,
......@@ -559,7 +577,6 @@ begin
irq_tdc_dma4_i => irq_dma(3),
irq_tdc_dma5_i => irq_dma(4)
);
end generate gen_enable_eic;
gen_disable_eic : if not g_use_fifo_readout and not g_use_dma_readout generate
......@@ -600,21 +617,6 @@ begin
i2c_scl_oen_o <= sys_scl_oe_n;
i2c_scl_o <= sys_scl_out;
U_OnewireIF : gc_ds182x_readout
generic map (
g_CLOCK_FREQ_KHZ => 62500,
g_USE_INTERNAL_PPS => true)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
pps_p_i => '0',
onewire_b => onewire_b,
id_o(63 downto 32) => regs_ow_in.tdc_ow_id_h_i,
id_o(31 downto 0) => regs_ow_in.tdc_ow_id_l_i,
temper_o => regs_ow_in.tdc_ow_temp_i,
id_read_o => regs_ow_in.tdc_ow_csr_valid_i);
gen_use_fake_timestamps : if g_use_fake_timestamps_for_sim generate
process(sim_timestamp_i, sim_timestamp_valid_i)
......
hdl/rtl/local_pps_gen.vhd
View file @ d50ff50a
......@@ -13,7 +13,6 @@
-- File local_pps_gen.vhd |
-- |
-- Description Generates one pulse every second synchronously with the ACAM reference clock. |
-- The phase with the reference clock can be adjusted (eva: think that is not needed)|
-- It also keeps track of the UTC time based on the local clock. |
-- If there is no White Rabbit synchronization, this unit is the source of UTC timing|
-- in the design.
......@@ -65,8 +64,8 @@ entity local_pps_gen is
-- Signals from the reg_ctrl unit
load_utc_p_i : in std_logic; -- enables loading of the local UTC time with starting_utc_i value
starting_utc_i : in std_logic_vector(g_width-1 downto 0); -- value coming from the GN4124/VME
pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
-- with respect to reference clock
--pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
-- with respect to reference clock
-- OUTPUTS
-- Signal to data_formatting and reg_ctrl units
......@@ -82,7 +81,7 @@ end local_pps_gen;
--=================================================================================================
architecture rtl of local_pps_gen is
constant constant_delay : unsigned(g_width-1 downto 0) := x"00000004";
constant constant_delay : std_logic_vector(g_width-1 downto 0) := x"00000004";
signal local_utc : unsigned(g_width-1 downto 0);
signal one_hz_p_pre : std_logic;
signal one_hz_p_post : std_logic;
......@@ -168,14 +167,14 @@ begin
(clk_i => clk_i,
rst_i => rst_i,
counter_load_i => one_hz_p_pre,
counter_top_i => total_delay,
counter_top_i => constant_delay,
-------------------------------------------
counter_is_zero_o => one_hz_p_post,
counter_o => open);
-------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
total_delay <= std_logic_vector(unsigned(pulse_delay_i)+constant_delay);
--total_delay <= std_logic_vector(unsigned(pulse_delay_i)+constant_delay);
local_utc_p_o <= one_hz_p_post;
......
hdl/rtl/reg_ctrl.vhd
View file @ d50ff50a
......@@ -54,11 +54,12 @@
-- Standard library
library IEEE;
use IEEE.std_logic_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use IEEE.std_logic_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.reg_ctrl_pkg.all; -- reg map
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
......@@ -94,7 +95,6 @@ entity reg_ctrl is
-- Signals not used so far
core_status_i : in std_logic_vector(g_width-1 downto 0); -- TDC core status word
irq_code_i : in std_logic_vector(g_width-1 downto 0); -- TDC core interrupt code word
-- White Rabbit status
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); --
......@@ -105,7 +105,7 @@ entity reg_ctrl is
acam_config_o : out config_vector;
-- Signals to the data_engine unit: TDC core functionality
activate_acq_p_o : out std_logic; -- activates tstamps aquisition from ACAM
activate_acq_p_o : out std_logic; -- activates tstamps acquisition from ACAM
deactivate_acq_p_o : out std_logic; -- activates ACAM configuration readings/ writings
acam_wr_config_p_o : out std_logic; -- enables writing to ACAM regs 0-7, 11, 12, 14
acam_rdbk_config_p_o : out std_logic; -- enables reading of ACAM regs 0-7, 11, 12, 14
......@@ -121,15 +121,16 @@ entity reg_ctrl is
-- Signals to the clks_resets_manager unit
send_dac_word_p_o : out std_logic; -- initiates the reconfiguration of the DAC
dac_word_o : out std_logic_vector(23 downto 0);
send_dac_word_p_o : out std_logic; -- initiates the reconfiguration of the DAC
dac_word_o : out std_logic_vector(23 downto 0);
-- Signal to the one_hz_gen unit
load_utc_p_o : out std_logic;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
-- Signals to the EIC unit
irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0); -- threshold in number of timestamps
irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0); -- threshold in number of ms
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0); -- for debug only
-- Signal to the TDC mezzanine board
acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0); -- enables all five input channels
......@@ -137,9 +138,6 @@ entity reg_ctrl is
-- White Rabbit control
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0); --
-- Signal to the acam_timecontrol_interface unit -- eva: i think it s not needed
start_phase_o : out std_logic_vector(g_width-1 downto 0);
int_flag_delay_o : out std_logic_vector(15 downto 0)
);
......@@ -153,8 +151,8 @@ architecture rtl of reg_ctrl is
signal acam_config : config_vector;
signal reg_adr, reg_adr_pipe0 : std_logic_vector(7 downto 0);
signal starting_utc, acam_inputs_en, start_phase : std_logic_vector(g_width-1 downto 0);
signal ctrl_reg, one_hz_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
signal starting_utc, acam_inputs_en : std_logic_vector(g_width-1 downto 0);
signal ctrl_reg, local_pps_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
signal irq_time_threshold : std_logic_vector(g_width-1 downto 0);
signal clear_ctrl_reg, send_dac_word_p : std_logic;
signal dac_word : std_logic_vector(23 downto 0);
......@@ -331,8 +329,6 @@ begin
-- o irq_time_threshold : for the activation of GN4124/VME interrupts based on the time elapsed
-- o starting_utc : definition of the current UTC time
-- o starting_utc : definition of the current UTC time
-- o one_hz_phase : eva: think it s not used
-- o start_phase : eva: think it s not used
TDCcore_config_reg_reception : process (clk_tdc_i)
begin
......@@ -340,11 +336,9 @@ begin
if rst_tdc_n_i = '0' then
acam_inputs_en <= (others => '0');
starting_utc <= (others => '0');
start_phase <= (others => '0');
one_hz_phase <= (others => '0');
wrabbit_ctrl_reg <= (others => '0');
irq_tstamp_threshold <= x"00000001"; -- default 256 timestamps: full memory
irq_time_threshold <= x"00000001"; -- default 200 ms
irq_tstamp_threshold <= x"00000001"; -- default 256 timestamps: full memory
irq_time_threshold <= x"00000001"; -- default 200 ms
dac_word <= c_DEFAULT_DAC_WORD; -- default DAC Vout = 1.65
gen_fake_ts_enable_o <= '0';
......@@ -361,14 +355,6 @@ begin
acam_inputs_en <= wb_in.dat;
end if;
if reg_adr = c_START_PHASE_ADR then
start_phase <= wb_in.dat;
end if;
if reg_adr = c_ONE_HZ_PHASE_ADR then
one_hz_phase <= wb_in.dat;
end if;
if reg_adr = c_IRQ_TSTAMP_THRESH_ADR then
irq_tstamp_threshold <= wb_in.dat;
end if;
......@@ -390,7 +376,6 @@ begin
gen_fake_ts_channel_o <= wb_in.dat(30 downto 28);
gen_fake_ts_period_o <= wb_in.dat(27 downto 0);
end if;
if reg_adr = c_TEST1_ADR then
int_flag_delay_o <= wb_in.dat(15 downto 0);
......@@ -402,8 +387,6 @@ begin
-- -- -- -- -- -- -- -- -- -- -- --
starting_utc_o <= starting_utc;
acam_inputs_en_o <= acam_inputs_en;
start_phase_o <= start_phase;
one_hz_phase_o <= one_hz_phase;
irq_tstamp_threshold_o <= irq_tstamp_threshold;
irq_time_threshold_o <= irq_time_threshold;
dac_word_o <= dac_word;
......@@ -449,7 +432,7 @@ begin
acam_rdbk_start01_p_o <= ctrl_reg(7);
acam_rst_p_o <= ctrl_reg(8);
load_utc_p_o <= ctrl_reg(9);
send_dac_word_p <= ctrl_reg(11);
send_dac_word_p <= ctrl_reg(11); -- not used
-- ctrl_reg bits 12 to 31 not used for the moment!
-- -- -- -- -- -- -- -- -- -- -- --
......@@ -472,7 +455,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Delivery of ACAM and TDC core Readback Registers --
-- HOST Reading of ACAM and TDC core registers --
---------------------------------------------------------------------------------------------------
-- TDCcore_ctrl_reg_reception: Delivery to the GN4124/VME interface of all the readable registers,
-- including those of the ACAM and the TDC core.
......@@ -529,8 +512,7 @@ begin
-- regs written by the GN4124/VME interface
starting_utc when c_STARTING_UTC_ADR,
acam_inputs_en when c_ACAM_INPUTS_EN_ADR,
start_phase when c_START_PHASE_ADR,
x"C000FFEE" when c_ONE_HZ_PHASE_ADR, -- ref for test
x"C000FFEE" when c_C000FFEE_BREAK_ADR, -- ref for test
irq_tstamp_threshold when c_IRQ_TSTAMP_THRESH_ADR,
irq_time_threshold when c_IRQ_TIME_THRESH_ADR,
x"00" & dac_word when c_DAC_WORD_ADR,
......@@ -538,14 +520,10 @@ begin
with reg_adr_pipe0 select dat_out_comb3 <=
-- regs written locally by the TDC core units
local_utc_i when c_LOCAL_UTC_ADR,
irq_code_i when c_IRQ_CODE_ADR,
x"00000000" when c_WR_INDEX_ADR,
core_status_i when c_CORE_STATUS_ADR,
local_utc_i when c_CURRENT_UTC_ADR,
-- White Rabbit regs
wrabbit_status_reg_i when c_WRABBIT_STATUS_ADR,
wrabbit_ctrl_reg when c_WRABBIT_CTRL_ADR,
x"00000000" when c_DEACT_CHAN_ADR,
-- others
x"00000000" when others;
......
hdl/rtl/tdc_core_pkg.vhd
View file @ d50ff50a
This diff is collapsed.
hdl/rtl/timestamp_convert_filter.vhd
View file @ d50ff50a
......@@ -35,6 +35,7 @@ entity timestamp_convert_filter is
ts_offset_i : in t_tdc_timestamp_array(4 downto 0);
ts_o : out t_tdc_timestamp_array(4 downto 0);
ts_valid_o : buffer std_logic_vector(4 downto 0);
ts_valid_p_o: out std_logic_vector(4 downto 0);
ts_ready_i : in std_logic_vector(4 downto 0)
);
end timestamp_convert_filter;
......@@ -331,6 +332,8 @@ begin
end if;
end if;
end process;
ts_valid_p_o <= ts_valid_postseq;
end generate gen_channels;
......
hdl/rtl/timestamp_fifo.vhd
View file @ d50ff50a
......@@ -129,65 +129,6 @@ begin
raw_enable_o <= channel_reg_out.csr_raw_mode_o;
---------------------------------------------------------------------------------------------------
-- Tstamps subtraction to calculate rising timestap deltas --
---------------------------------------------------------------------------------------------------
-- Latching of the last rising edge tstamp
p_latch_ref_timestamp : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i = '0' then
ref_valid <= '0';
else
-- latch only the last rising edge tstamp
if (enable_i = '1' and timestamp_valid_i = '1') then
ref_valid <= '1';
ref_ts <= timestamp_i;
end if;
end if;
end if;
end process;
sub_valid <= ref_valid and timestamp_valid_i;
-- Tstamp pipelined subtractor
U_Subtractor : entity work.tdc_ts_sub
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
valid_i => sub_in_valid,
enable_i => enable_i,
a_i => timestamp_i,
b_i => ref_ts,
valid_o => sub_out_valid,
q_o => sub_result);
-- Deltas calculations
p_latch_deltas : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i = '0' then
sub_out_valid_latched <= '0';
else
if channel_reg_out.csr_delta_read_o = '1' then
sub_out_valid_latched <= '0';
channel_reg_in.delta1_i <= sub_result_latched.tai;
channel_reg_in.delta2_i <= sub_result_latched.coarse;
channel_reg_in.delta3_i <= x"00000" & sub_result_latched.frac;
end if;
if(sub_out_valid = '1') then
sub_out_valid_latched <= '1';
sub_result_latched <= sub_result;
end if;
end if;
end if;
end process;
channel_reg_in.csr_delta_ready_i <= sub_out_valid_latched;
gen_without_fifo_readout : if not g_USE_FIFO_READOUT generate
fifo_reg_slave_out <= c_DUMMY_WB_SLAVE_OUT;
fifo_reg_out <= c_tsf_out_registers_init_value;
......
hdl/syn/spec/wr_spec_tdc.xise
View file @ d50ff50a
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/spec/buildinfo_pkg.vhd
View file @ d50ff50a
......@@ -6,8 +6,8 @@ package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:6fa0c8c704d7778c5ae05683e55986f346bc2066" & LF
& "commit:ca5ace53d7d35580770a3b79359c4a80fdd9775d" & LF
& "syntool:modelsim" & LF
& "syndate:2019-10-01, 11:52 CEST" & LF
& "syndate:2019-11-12, 18:04 CET" & LF
& "synauth:Evangelia Gousiou" & LF;
end buildinfo_pkg;
hdl/testbench/spec/main.sv
View file @ d50ff50a
......@@ -15,53 +15,58 @@ typedef struct {
uint32_t coarse;
uint32_t frac;
uint32_t seq;
int slope;
int channel;
int slope;
int channel;
} fmc_tdc_timestamp_t;
typedef fmc_tdc_timestamp_t fmc_tdc_timestamp_queue_t[$];
class FmcTdcDriver;
CBusAccessor m_acc;
uint64_t m_base;
uint64_t m_base;
fmc_tdc_timestamp_queue_t m_queues[5];
// new
function new(CBusAccessor acc, uint64_t base, bit use_dma);
m_acc = acc;
m_base = base;
endfunction // new
endfunction
task automatic writel( uint32_t addr, uint32_t value );
// writel
task automatic writel(uint32_t addr, uint32_t value);
m_acc.write(addr + m_base ,value);
endtask // writel
endtask
// readl
task automatic readl( uint32_t addr, ref uint32_t value );
automatic uint64_t rv;
m_acc.read(addr + m_base , rv);
// $display("readl %x %x", addr+m_base, rv);
$display("[Info] readl %x: %x", addr+m_base, rv);
value = rv;
endtask // readl
endtask
// init
task automatic init();
uint32_t d;
$display("!!!base: %x", m_base);
$display("[Info] TDC core base addr: %x", m_base);
readl('h0, d);
if( d != 'h5344422d )
begin
$error("Can't read the SDB signature.");
begin
$error("[Error!] Can't read the SDB signature.");
$stop;
end
$display("address 0x20000: %x", d);
end
readl('h208c, d);
$display("!!!address 0x2208c: %x", d);
readl('h1000, d);
readl('h1004, d);
readl('h1008, d);
readl('h100C, d);
writel('h20a0, 1234); // set UTC
$display("[Info] Setting up TDC core..");
writel('h20a0, 1234); // set UTC
writel('h20fc, 1<<9); // load UTC
writel('h3004, 'h1f); // enable EIC irqs for all FIFO channels
......@@ -71,50 +76,49 @@ class FmcTdcDriver;
writel('h20fc, (1<<0)); // start acquisition
writel('h20bc, ((-1)<<1));
$display("FmcTdcDriver: acquisition started");
$display("[Info] TDC acquisition started");
endtask // init
endtask
// update
task automatic update();
automatic uint32_t csr, t[4];
for(int i = 0; i < 5; i++)
begin
begin
automatic uint32_t base = 'h5000 + i * 'h100;
automatic fmc_tdc_timestamp_t ts;
readl(base + `ADDR_TSF_FIFO_CSR, csr);
// $display("csr %x", csr);
$display("csr %x", csr);
if( ! (csr & `TSF_FIFO_CSR_EMPTY ) )
begin
readl(base + `ADDR_TSF_FIFO_R0, t[0]);
readl(base + `ADDR_TSF_FIFO_R1, t[1]);
readl(base + `ADDR_TSF_FIFO_R2, t[2]);
readl(base + `ADDR_TSF_FIFO_R3, t[3]);
ts.tai = t[0];
ts.coarse = t[1];
ts.frac = t[2] & 'hfff;
ts.slope = t[3] & 'h8 ? 1: 0;
ts.seq = t[3] >> 4;
ts.channel = i;
m_queues[i].push_back(ts);
begin
readl(base + `ADDR_TSF_FIFO_R0, t[0]);
readl(base + `ADDR_TSF_FIFO_R1, t[1]);
readl(base + `ADDR_TSF_FIFO_R2, t[2]);
readl(base + `ADDR_TSF_FIFO_R3, t[3]);
ts.tai = t[0];
ts.coarse = t[1];
ts.frac = t[2] & 'hfff;
ts.slope = t[3] & 'h8 ? 1: 0;
ts.seq = t[3] >> 4;
ts.channel = i;
m_queues[i].push_back(ts);
end
end // for (int i = 0; i < 5; i++)
endtask // update
endtask
endclass // FmcTdcDriver
//////////////// main ////////////////
module main;
// clk, rst
reg rst_n = 0;
reg clk_125m = 0, clk_20m = 0;
......@@ -126,7 +130,6 @@ module main;
rst_n = 1;
end
reg clk_acam = 0; // 31.25 MHz
reg clk_62m5 = 0;
......@@ -136,19 +139,20 @@ module main;
always@(posedge clk_62m5)
clk_acam <= ~clk_acam;
wire [3:0] tdc_addr;
wire [27:0] tdc_data;
reg [8:1] tdc_stop = 0;
wire tdc_start, tdc_start_dis;
wire [4:1] tdc_stop_dis;
// wires, regs
wire tdc_start, tdc_start_dis;
wire tdc_cs_n, tdc_oe_n, tdc_rd_n, tdc_wr_n;
wire tdc_err_flag, tdc_int_flag;
wire tdc_ef1, tdc_ef2;
wire [3:0] tdc_addr;
wire [27:0] tdc_data;
wire [4:1] tdc_stop_dis;
reg [8:1] tdc_stop = 0;
// ACAM model instantiation
tdc_gpx_model
#( .g_verbose(0) )
#( .g_verbose(1) )
ACAM
(
.PuResN(1'b1),
......@@ -179,12 +183,14 @@ module main;
.D(tdc_data)
);
// GN4124 model instantiation
IGN4124PCIMaster Host
(
);
// TDC core instantiation
wr_spec_tdc
#(
.g_simulation(1)
......@@ -218,112 +224,52 @@ module main;
.fmc0_tdc_start_from_fpga_o(tdc_start),
.fmc0_tdc_start_dis_o(tdc_start_dis),
.fmc0_tdc_stop_dis_o(tdc_stop_dis[1]),
`GENNUM_WIRE_SPEC_BTRAIN_REF(Host)
);
assign tdc_stop_dis[4] = tdc_stop_dis[1];
assign tdc_stop_dis[3] = tdc_stop_dis[1];
assign tdc_stop_dis[2] = tdc_stop_dis[1];
// IVHDWishboneMaster Host
// (
// .clk_i (DUT.clk_sys_62m5),
// .rst_n_i (DUT.rst_sys_62m5_n)
// );
initial
begin
CBusAccessor acc;
FmcTdcDriver drv;
const uint64_t tdc1_base = 'h20000;
uint64_t d;
acc = Host.get_accessor();
// initial
initial begin
CBusAccessor acc;
FmcTdcDriver drv;
const uint64_t tdc1_base = 'h20000;
uint64_t d;
acc = Host.get_accessor();
#10us;
#10us;
// reset
//$display("Un-reset FMCs...");
//acc.write('h02000c, 'h3);
acc.read('h20000, d);
$display("address 0x20000: %x", d);
acc.read('h22004, d);
$display("address 0x22004: %x", d);
acc.write('h2208c, 1234); // test
acc.read('h2208c, d);
$display("address 0x2208c: %x", d);
//acc.write('h22080, 1234); // starting UTC
//acc.write('h220fc, 1<<9); // load UTC
//acc.write('h22080, 1234); //
//acc.write('h220fc, 1<<9); //
//acc.write('h23004, 'h1f); //
//writel('h3004, 'h1f); // enable EIC irqs for all FIFO channels
//acc.write('h22084, 'h1f0000); //
//writel('h2084, 'h1f0000); // enable all ACAM inputs
//acc.write('h22090, 2); //
//writel('h2090, 2); // FIFO threshold = 2 ts
//acc.write('h22094, 2); //
//writel('h2094, 2); // FIFO threshold = 2 ms
//acc.write('h220FC, (1<<0)); //
//writel('h20fc, (1<<0)); // start acquisition
//acc.write('h220BC, ((-1)<<1)); //
//writel('h20bc, ((-1)<<1));
//writel('h20a0, 1234); // set UTC
//writel('h20fc, 1<<9); // load UTC
//writel('h3004, 'h1f); // enable EIC irqs for all FIFO channels
//writel('h2084, 'h1f0000); // enable all ACAM inputs
//writel('h2090, 2); // FIFO threshold = 2 ts
//writel('h2094, 2); // FIFO threshold = 2 ms
//writel('h20fc, (1<<0)); // start acquisition
//writel('h20bc, ((-1)<<1));
// test read
acc.read('h2208c, d);
// device instantiation
drv = new (acc, 'h20000, 0 );
drv.init();
$display("Start operation");
$display("[Info] Start operation");
fork
forever begin
drv.update();
#10us;
end
forever begin
#700ns;
tdc_stop[1] <= 1;
#300ns;
tdc_stop[1] <= 0;
end
forever begin
drv.update();
#10us;
end
forever begin
#700ns;
tdc_stop[1] <= 1;
#300ns;
tdc_stop[1] <= 0;
end
join
end
end
endmodule // main
......
hdl/testbench/spec/wave.do
View file @ d50ff50a
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hdl/top/spec/wr_spec_tdc.vhd
View file @ d50ff50a
......@@ -71,35 +71,6 @@
-- | | |
-- |___________________________________________________________________________| |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Grzegorz Daniluk (Grzegorz.Daniluk@cern.ch)
-- Date 06/2014 |
-- Version v6 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v1 GP First version |
-- 06/2012 v2 EG Revamping; Comments added, signals renamed |
-- removed LEDs from top level |
-- new GN4124 core integrated |
-- carrier 1 wire master added |
-- mezzanine I2C master added |
-- mezzanine 1 wire master added |
-- interrupts generator added |
-- changed generation of rst_125m_mezz |
-- DAC reconfiguration+needed regs added |
-- 06/2012 v3 EG Changes for v2 of TDC mezzanine |
-- Several pinout changes, |
-- acam_ref_clk LVDS instead of CMOS, |
-- no PLL_LD only PLL_STATUS |
-- 04/2013 v4 EG added SDB; fixed bugs in data_formatting; added carrier CSR information |
-- 01/2014 v5 EG added VIC and EIC in the TDC mezzanine |
-- 06/2014 v6 EG added White Rabbit support |
-- 12/2017 v7 GD Top file reorganized to benefit from WRPC Board wrapper. |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -666,7 +637,7 @@ begin
g_simulation => g_simulation,
g_with_direct_readout => false, -- for embedded applications, like WRTD
g_use_dma_readout => g_use_dma_readout,
g_use_fifo_readout => true,
g_use_fifo_readout => TRUE,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
port map (
clk_sys_i => clk_sys_62m5,
......
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