design uses submodules only (instead of HDD repo); wrpc links some debug clocks to fasec_hwmodule for debugging

after reimportation, synthesis and implementation OK; still work needed on timing constraints though

design goes succesfully through synthesis and implementation; timing constraints not met caused by clk_fpga_1 - ext. 10 MHz - which should not cause problems

2/3 ocores i2c master IPs have their interrupt connect to the PS irq_f2p for linux driver integration

xadc dma still in design; made xadc input signals external for Zynq floorplan routing (requirement\!)

xadc dma; fasec_hwtest updated to v2.8.1 (spi, memory-mapping); tcl script for compile time and commit id

No VHDL/IP changes but new SDK workspace (..sdk2) for Periph-test; by adding 2ns analogue delay and some software fixes FASEC-2 finally PASSED EmacPsDmaIntrExample test

first functional EDA03287 IP core implemented - IO read/write possible for both FMC slots; software updated accordingly