xadc dma still in design; made xadc input signals external for Zynq floorplan...
xadc dma still in design; made xadc input signals external for Zynq floorplan routing (requirement\!)
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- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/sgmii_adapt/system_design_gig_ethernet_pcs_pma_0_0_clock_div.vhd 191 additions, 0 deletions...dapt/system_design_gig_ethernet_pcs_pma_0_0_clock_div.vhd
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- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/sgmii_adapt/system_design_gig_ethernet_pcs_pma_0_0_tx_rate_adapt.vhd 240 additions, 0 deletions.../system_design_gig_ethernet_pcs_pma_0_0_tx_rate_adapt.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/system_design_gig_ethernet_pcs_pma_0_0.vhd 308 additions, 0 deletions..._pma_0_0/synth/system_design_gig_ethernet_pcs_pma_0_0.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/system_design_gig_ethernet_pcs_pma_0_0_block.vhd 677 additions, 0 deletions..._0/synth/system_design_gig_ethernet_pcs_pma_0_0_block.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/system_design_gig_ethernet_pcs_pma_0_0_clocking.vhd 238 additions, 0 deletions...synth/system_design_gig_ethernet_pcs_pma_0_0_clocking.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/system_design_gig_ethernet_pcs_pma_0_0_gt_common.vhd 238 additions, 0 deletions...ynth/system_design_gig_ethernet_pcs_pma_0_0_gt_common.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/system_design_gig_ethernet_pcs_pma_0_0_reset_sync.vhd 175 additions, 0 deletions...nth/system_design_gig_ethernet_pcs_pma_0_0_reset_sync.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/system_design_gig_ethernet_pcs_pma_0_0_resets.vhd 105 additions, 0 deletions...0/synth/system_design_gig_ethernet_pcs_pma_0_0_resets.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/system_design_gig_ethernet_pcs_pma_0_0_support.vhd 377 additions, 0 deletions.../synth/system_design_gig_ethernet_pcs_pma_0_0_support.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_gig_ethernet_pcs_pma_0_0/synth/system_design_gig_ethernet_pcs_pma_0_0_sync_block.vhd 174 additions, 0 deletions...nth/system_design_gig_ethernet_pcs_pma_0_0_sync_block.vhd
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