resynthesised because of some bitstream version problems (c6c7adfe) · Commits · Projects / FPGA and ARM SoC FMC Carrier FASEC · GitLab

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FPGA and ARM SoC FMC Carrier FASEC
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c6c7adfe

Commit c6c7adfe authored 8 years ago by

Pieter Van Trappen

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resynthesised because of some bitstream version problems

parent ae4bd82e

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Changes 5

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FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v2_9/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd 4 additions, 3 deletions

...c_hwtest_v2_9/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v2_9/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd.old 0 additions, 438 deletions

...test_v2_9/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd.old
FASEC_prototype.srcs/tcl/set_registers.tcl 6 additions, 4 deletions

FASEC_prototype.srcs/tcl/set_registers.tcl
FASEC_prototype.xpr 22 additions, 0 deletions

FASEC_prototype.xpr
firmware/system_design_wrapper.bit 0 additions, 0 deletions

firmware/system_design_wrapper.bit

with 32 additions and 445 deletions

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