Now using an FSM to hadel pulse repetition and rejection. Thermal model constant decrement steps are now a generic rather than a signal

added modified version of burst controller that should work for 1.2us pulses. File is not stricly usable yet as it uses a different length array for thermal model, than the generic burst control module. This array should be turned into a generic value in entity for the the burst module to be generic enough

Modified conv_regs entity and component declaration according to new conv_regs.vhd from previous commit

conv_regs.vhd had some minor inconsistencies with conv_regs.wb due to some manual changes. conv_regs.wb has now been modified to match a more recent one on remotes/origin/wr-n-th and then conv_regs has been regenerated without manual intervention

Small modifications to account for very short pulses of 250ns. Previously module would not work properly for the required 2MHz frequency

Updated top file and burt control module with little modifications. NOTE LED sequence is fixed at certain pattern for bitstream debugging

Modified top files to support all modifications in register map plus the new burst controller. Note that the burst controller supported in this commit is the one that averages frequency over 1000 pulses

Added new registers to count TTL pulses and Blocking pulses separately for each channel, instead of counting the OR of the two

The description of the CSR.RST bit has been made clearer to show that it is only
active when CSR.RST_UNLOCK = '1'.

OSWR also now contains 32 bits, to allow for 32 switches in addition to the
existing 8 general-purpose ones.

The 125 MHz domain registers are loaded only once the 20 MHz clock domain
registers are loaded. Like this, we avoid having different values in the
registers in the two clock domains.

This makes the doc and module more generic. The modification will be made in
the code as well.

Also added link to OHWR Wiki page for project examples in the same section.

This is to make sure no readouts of erroneous values from this registers
occur due to the register value not being stable at the time the WB read
cycle is requested.

The pulse synchronizer for the latest timestamp load signal implemented
as part of the previous commit was not working, due to a wrongly-connected
signal. The appropriate signal was connected and the pulse synchronization
mechanism seems to work.

The pulse synchronizer makes sure the load pulse to the 125 MHz clock
domain registers generates a pulse to load the registers in the 20 MHz
clock domain, which are the registers that are read via I2C.