File to handle high frequency bursts in a dynamic way, on a pulse by pulse basis

0161ea17 · Denia Bouhired-Ferrag · e578169c · 0161ea17
Commit 0161ea17 authored Dec 07, 2016 by Denia Bouhired-Ferrag
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conv_dyn_burst_ctrl.vhd modules/conv_dyn_burst_ctrl.vhd +212 -0

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--- a/modules/conv_dyn_burst_ctrl.vhd
+++ b/modules/conv_dyn_burst_ctrl.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Burst mode control module
+--==============================================================================
+--
+-- author: Denia Bouhired (denia.bouhired@cern.ch)
+--
+-- Date of creation: 19-09-2016 
+--
+-- version: 1.0
+--
+-- description:
+-- This module serves as a burst mode controller. When pulses of pre-defined length (250 ns) arrive, this module evaluates whether the module needs some "cool-off" time every burst_length number of pulses. Burst-length is the maximum number of pulses the board can handle at maximum frequency 2MHz and is determined through direct laboratory measurements on board prototypes. It is considered a pure hardware limitation. For version 1 this is set to absolute maximum of 1000 but the generic value can be changed for lower values.
+
+-- dependencies:
+--    
+
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    19-09-2016   Denia Bouhired     File created.
+--		
+--==============================================================================
+-- TODO: -
+--==============================================================================
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+
+use work.conv_common_gw_pkg.all;
+
+
+
+entity conv_dyn_burst_ctrl is
+	generic
+	(
+		g_pwidth : natural range 2 to 40 	:= 5; 
+		-- Duty cycle divider: D = 1/g_duty_cycle_div
+		g_duty_cycle_div : natural 			:= 18;
+		g_1_pulse_energ			:in unsigned (15 downto 0) := x"A410";
+		g_max_temp_rise			:in unsigned (39 downto 0) := x"174876E800" 
+	);
+	port
+	(
+    -- Clock and active-low reset inputs
+    clk_i        	: in  std_logic;
+    rst_n_i      	: in  std_logic;
+	
+	-- Enable input, pulse generation is enabled when '1'
+    en_i         	 	: in  std_logic;
+	pulse_burst_i 		: in std_logic;
+	
+	temp_rise_c			: out unsigned (39 downto 0) ;
+	pulse_burst_o		: out std_logic;
+	
+	-- Burst error output, pulses high for one clock cycle when a pulse arrives
+    -- within a burst rejection phase
+    burst_err_p_o : out std_logic	
+	
+	);
+	end entity conv_dyn_burst_ctrl;
+	
+	architecture behav of conv_dyn_burst_ctrl is
+	
+	type t_temp_decre is array (0 to 6) of integer; 
+	
+	-----signals declaration----------
+	
+	signal temp_decre  : t_temp_decre := (0, 1668, 200, 38, 20, 4, 100); 
+
+	signal burst_ctrl_rst			: std_logic;
+	signal pulse_train_in 			: std_logic;
+	signal temp_rise				: unsigned (39 downto 0) ;
+	signal test				: integer ;
+	signal temp_fall				: unsigned (39 downto 0) ;
+	signal single_cycle_cnt			: integer;
+	signal five_cycle_cnt			: integer;
+	
+	signal pulse_train_in_d0 		   : std_logic;
+	signal pulse_train_in_r_edge_p   : std_logic;
+	signal pulse_train_in_f_edge_p   : std_logic;
+	
+	
+	begin
+	
+	  -- Generate the pulse on rising edge of pulse_burst_i
+  p_pulse_redge: process (clk_i, burst_ctrl_rst, pulse_burst_i, pulse_train_in_r_edge_p)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+			burst_err_p_o <= '0';
+	elsif (en_i = '1') then
+	if (burst_ctrl_rst = '1')  then
+		if falling_edge(pulse_burst_i) then       
+			pulse_train_in 		<= '0';
+		end if;
+		
+			
+		burst_err_p_o <= '0';
+		if pulse_train_in_r_edge_p = '1' then
+			burst_err_p_o <= '1';
+		end if;
+		 
+		
+    elsif (burst_ctrl_rst = '0') then
+		--if (pulse_burst_i = '0') then         
+			pulse_train_in 		<= pulse_burst_i; --re-activate output only if input line is off
+		--end if;
+        
+	end if;
+	end if;
+	end if;
+  end process p_pulse_redge;
+  
+    p_pulse_redge_detect : process (clk_i) is
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+        pulse_train_in_d0       <= '0';
+        pulse_train_in_r_edge_p <= '0';
+      elsif (en_i='1') then
+        pulse_train_in_d0       <= pulse_burst_i;
+        pulse_train_in_r_edge_p <= pulse_burst_i and (not pulse_train_in_d0);
+        pulse_train_in_f_edge_p <= (not pulse_burst_i) and pulse_train_in_d0;
+      end if;
+    end if;
+  end process p_pulse_redge_detect;
+  
+  
+pulse_burst_o <= pulse_train_in;
+temp_rise_c <=temp_rise;
+  
+  p_five_cycle_cnt : process(clk_i)
+  begin
+  if rising_edge(clk_i) then
+		if rst_n_i = '0' then
+				single_cycle_cnt <= 1;
+				five_cycle_cnt   <= 1;
+		else 
+			
+			
+		if pulse_train_in_r_edge_p = '1' and burst_ctrl_rst /= '1' then	
+				single_cycle_cnt <= 1;
+				five_cycle_cnt   <= 1;
+		elsif pulse_train_in = '0' then
+				single_cycle_cnt <= single_cycle_cnt+1;
+				if single_cycle_cnt = 5 then
+					if five_cycle_cnt < 7 then
+						five_cycle_cnt <= five_cycle_cnt + 1;
+					end if;
+					single_cycle_cnt <= 1;
+					--temp_fall <= to_unsigned(temp_decre(five_cycle_cnt), 40);
+				end if;
+				
+		end if;
+		end if;
+	end if;
+  end process p_five_cycle_cnt;
+  
+
+  p_thermal_sim : process (clk_i, five_cycle_cnt)
+  begin	    
+  if rising_edge(clk_i) then
+			
+			
+      if rst_n_i = '0' then
+			temp_rise <= (others => '0');
+			burst_ctrl_rst 	 <= '1';
+
+	  else
+			if signed(temp_rise) >= 0 and (signed(temp_rise) <= signed(g_max_temp_rise)) then
+					
+				if pulse_burst_i = '0' then
+					burst_ctrl_rst <= '0';
+				end if;
+				if pulse_train_in_r_edge_p = '1' and burst_ctrl_rst /= '1' then 	-- temperature less than maximum
+					temp_rise <= temp_rise + g_1_pulse_energ;
+					
+				elsif signed(temp_rise) > 0 and pulse_train_in = '0' then		--temperature fall between pulses
+					test <= temp_decre(five_cycle_cnt-1);
+						if temp_rise > 190 then
+							temp_rise <= temp_rise - to_unsigned(temp_decre(five_cycle_cnt-1), 40);
+						else
+							temp_rise <= (others => '0');
+						end if;
+				end if;
+			elsif (signed(temp_rise) > signed(g_max_temp_rise)) and pulse_train_in = '0' then -- and (pulse_train_in_f_edge_p = '1') then
+				burst_ctrl_rst <= '1'; 
+				temp_rise <= temp_rise - temp_decre(five_cycle_cnt-1);
+			end if;
+		
+	  end if;
+	end if;
+	end process p_thermal_sim;
+	
+	
+	
+	end architecture behav;
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