Add simulation model for conv_man_trig

21f76124 · Theodor-Adrian Stana · 183c2bae · 21f76124 · 21f76124 · 21f76124
Commit 21f76124 authored Aug 22, 2014 by Theodor-Adrian Stana
5 changed files
--- a/sim/conv_man_trig/Makefile
+++ b/sim/conv_man_trig/Makefile
--- a/sim/conv_man_trig/Manifest.py
+++ b/sim/conv_man_trig/Manifest.py
+target = "xilinx"
+action = "simulation"
+
+files = [
+        "testbench.vhd"
+    ]
+
+modules = { "local" : "../../" }
--- a/sim/conv_man_trig/run.do
+++ b/sim/conv_man_trig/run.do
+vlib work
+
+vsim -t 1ps -voptargs="+acc" -lib work work.testbench
+
+radix -hexadecimal
+#add wave *
+do wave.do
+
+run 100 us
+wave zoomfull
--- a/sim/conv_man_trig/testbench.vhd
+++ b/sim/conv_man_trig/testbench.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Testbench for the manual trigger module
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2014-01-30
+--
+-- version: 1.0
+--
+-- description:
+--
+-- dependencies:
+--
+-- references:
+--
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2014-01-30   Theodor Stana     File created
+--==============================================================================
+-- TODO: -
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+use work.conv_common_gw_pkg.all;
+
+entity testbench is
+end entity testbench;
+
+
+architecture behav of testbench is
+
+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+  constant c_clk_per : time := 50 ns;
+  constant c_reset_width : time := 31 ns;
+
+  --============================================================================
+  -- Functions and procedures
+  --============================================================================
+  procedure f_mantrig
+  (
+    constant chan   : in  integer;
+    signal   mpt    : out std_logic_vector(7 downto 0);
+    signal   mpt_wr : out std_logic
+  ) is
+  begin
+    wait for 1 us;
+    mpt    <= x"de";
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt    <= x"ad";
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt    <= x"be";
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt    <= x"ef";
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt    <= std_logic_vector(to_unsigned(chan, 8));
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+  end procedure;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal clk20     : std_logic := '0';
+  signal rst_n     : std_logic;
+  signal mpt_wr    : std_logic;
+  signal mpt_wr_d0 : std_logic;
+  signal mpt_ld    : std_logic;
+  signal mpt       : std_logic_vector(7 downto 0);
+  signal trig_man  : std_logic_vector(6 downto 1);
+  signal pulse     : std_logic_vector(6 downto 1);
+  signal gf_n        : std_logic;
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  --============================================================================
+  -- Generate clock and reset signals
+  --============================================================================
+  p_clk: process
+  begin
+    clk20 <= not clk20;
+    wait for c_clk_per/2;
+  end process p_clk;
+
+  p_rst_n: process
+  begin
+    rst_n <= '0';
+    wait for c_reset_width;
+    rst_n <= '1';
+    wait;
+  end process p_rst_n;
+
+  --============================================================================
+  -- Instantiate DUT and conv_pulse_gen blocks it drives
+  --============================================================================
+  -- First, the DUT
+  cmp_dut : conv_man_trig
+    generic map
+    (
+      g_nr_chan => 6,
+      g_pwidth  => 10
+    )
+    port map
+    (
+      clk_i    => clk20,
+      rst_n_i  => rst_n,
+
+      reg_ld_i => mpt_ld,
+      reg_i    => mpt,
+
+      trig_o   => trig_man
+    );
+
+  -- Then, the pulse generators with a generate statement
+  gen_pulse_gens : for i in 1 to 6 generate
+    cmp_pulse_gen : conv_pulse_gen
+      generic map
+      (
+        g_with_fixed_pwidth => true,
+        g_pwidth => 24,
+        g_duty_cycle_div => 5
+      )
+      port map
+      (
+        clk_i     => clk20,
+        rst_n_i   => rst_n,
+        gf_en_n_i => gf_n,
+        en_i      => '1',
+        trig_a_i  => trig_man(i),
+        pulse_o   => pulse(i)
+      );
+  end generate gen_pulse_gens;
+
+  --============================================================================
+  -- Some stimuli for the DUT
+  --============================================================================
+  p_mpt_ld : process (clk20)
+  begin
+    if rising_edge(clk20) then
+      if rst_n = '0' then
+        mpt_ld    <= '0';
+        mpt_wr_d0 <= '0';
+      else
+        mpt_wr_d0 <= mpt_wr;
+        mpt_ld    <= mpt_wr and not mpt_wr_d0;
+      end if;
+    end if;
+  end process;
+
+  p_stim : process
+  begin
+    mpt_wr <= '0';
+    mpt    <= (others => '0');
+    --------------------------
+    -- No glitch filt
+    --------------------------
+    gf_n <= '1';
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    --------------------------
+    -- With glitch filt
+    --------------------------
+    gf_n <= '0';
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    gf_n <= '1';
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    --------------------------
+    -- No glitch filt
+    --------------------------
+    gf_n <= '1';
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    gf_n <= '0';
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    wait;
+  end process p_stim;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/sim/conv_man_trig/wave.do
+++ b/sim/conv_man_trig/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk20
+add wave -noupdate /testbench/rst_n
+add wave -noupdate /testbench/mpt_ld
+add wave -noupdate /testbench/mpt
+add wave -noupdate /testbench/trig_man
+add wave -noupdate -expand /testbench/pulse
+add wave -noupdate -divider DUT
+add wave -noupdate /testbench/cmp_dut/state
+add wave -noupdate /testbench/cmp_dut/pass
+add wave -noupdate /testbench/cmp_dut/chnr
+add wave -noupdate /testbench/cmp_dut/cnt
+add wave -noupdate /testbench/cmp_dut/trig_o
+add wave -noupdate -divider {glitch filt}
+add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate -divider {pulse gen}
+add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_on
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {218986486 ps} 0} {{Cursor 2} {74966216 ps} 0}
+configure wave -namecolwidth 383
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {315 us}