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conv-common-gw
Commit a8c0d688 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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conv_regs.vhd had some minor inconsistencies with conv_regs.wb due to some… 

conv_regs.vhd had some minor inconsistencies with conv_regs.wb due to some manual changes. conv_regs.wb has now been modified to match a more recent one on remotes/origin/wr-n-th and then conv_regs has been regenerated without manual intervention
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modules/conv_regs.h
View file @ a8c0d688
/*
Register definitions for slave core: Converter board registers
* File : C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs.h
* Author : auto-generated by wbgen2 from C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs.wb
* Created : 12/16/16 14:31:04
* File : conv_regs.h
* Author : auto-generated by wbgen2 from conv_regs.wb
* Created : 12/20/16 12:38:49
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_C:\USERS\DEBOUHIR\WORK\CONV-TTL-BLO\CONV-TTL-BLO\CONV-TTL-BLO-GW\IP_CORES\CONV-COMMON-GW\MODULES\CONV_REGS_WB
#define __WBGEN2_REGDEFS_C:\USERS\DEBOUHIR\WORK\CONV-TTL-BLO\CONV-TTL-BLO\CONV-TTL-BLO-GW\IP_CORES\CONV-COMMON-GW\MODULES\CONV_REGS_WB
#ifndef __WBGEN2_REGDEFS_CONV_REGS_WB
#define __WBGEN2_REGDEFS_CONV_REGS_WB
#include <inttypes.h>
......@@ -275,16 +275,16 @@
/* definitions for register: OSWR */
/* definitions for field: Switch state in reg: OSWR */
#define REG_MSWR_SWITCHES_MASK WBGEN2_GEN_MASK(0, 32)
#define REG_MSWR_SWITCHES_SHIFT 0
#define REG_MSWR_SWITCHES_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define REG_MSWR_SWITCHES_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
#define REG_OSWR_SWITCHES_MASK WBGEN2_GEN_MASK(0, 32)
#define REG_OSWR_SWITCHES_SHIFT 0
#define REG_OSWR_SWITCHES_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define REG_OSWR_SWITCHES_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: 32 least significant bits of DS18B20U */
/* definitions for register: UIDLR */
/* definitions for register: 32 most significant bits of DS18B20U */
/* definitions for register: UIDHR */
/* definitions for register: Board temperature */
/* definitions for register: TEMPR */
/* [0x0]: REG BIDR */
#define REG_REG_BIDR 0x00000000
/* [0x4]: REG SR */
......@@ -368,11 +368,11 @@
/* [0xa0]: REG LSR */
#define REG_REG_LSR 0x000000a0
/* [0xa4]: REG OSWR */
#define REG_REG_MSWR 0x000000a4
/* [0xa8]: REG 32 least significant bits of DS18B20U */
#define REG_REG_DS18B20U_ID_LSB 0x000000a8
/* [0xac]: REG 32 most significant bits of DS18B20U */
#define REG_REG_DS18B20U_ID_MSB 0x000000ac
/* [0xb0]: REG Board temperature */
#define REG_REG_DS18B20U_TEMP 0x000000b0
#define REG_REG_OSWR 0x000000a4
/* [0xa8]: REG UIDLR */
#define REG_REG_UIDLR 0x000000a8
/* [0xac]: REG UIDHR */
#define REG_REG_UIDHR 0x000000ac
/* [0xb0]: REG TEMPR */
#define REG_REG_TEMPR 0x000000b0
#endif
modules/conv_regs.htm
View file @ a8c0d688
......@@ -76,9 +76,9 @@
<span style="margin-left: 20px; ">3.40. <A href="#sect_3_40">CH6LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.41. <A href="#sect_3_41">LSR</a></span><br/>
<span style="margin-left: 20px; ">3.42. <A href="#sect_3_42">OSWR</a></span><br/>
<span style="margin-left: 20px; ">3.43. <A href="#sect_3_43">32 least significant bits of DS18B20U</a></span><br/>
<span style="margin-left: 20px; ">3.44. <A href="#sect_3_44">32 most significant bits of DS18B20U</a></span><br/>
<span style="margin-left: 20px; ">3.45. <A href="#sect_3_45">Board temperature</a></span><br/>
<span style="margin-left: 20px; ">3.43. <A href="#sect_3_43">UIDLR</a></span><br/>
<span style="margin-left: 20px; ">3.44. <A href="#sect_3_44">UIDHR</a></span><br/>
<span style="margin-left: 20px; ">3.45. <A href="#sect_3_45">TEMPR</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -803,13 +803,13 @@ LSR
REG
</td>
<td >
<A href="#MSWR">OSWR</a>
<A href="#OSWR">OSWR</a>
</td>
<td class="td_code">
reg_mswr
reg_oswr
</td>
<td class="td_code">
MSWR
OSWR
</td>
</tr>
<tr class="tr_odd">
......@@ -820,13 +820,13 @@ MSWR
REG
</td>
<td >
<A href="#DS18B20U_ID_LSB">32 least significant bits of DS18B20U</a>
<A href="#UIDLR">UIDLR</a>
</td>
<td class="td_code">
reg_ds18b20u_id_lsb
reg_uidlr
</td>
<td class="td_code">
DS18B20U_ID_LSB
UIDLR
</td>
</tr>
<tr class="tr_even">
......@@ -837,13 +837,13 @@ DS18B20U_ID_LSB
REG
</td>
<td >
<A href="#DS18B20U_ID_MSB">32 most significant bits of DS18B20U</a>
<A href="#UIDHR">UIDHR</a>
</td>
<td class="td_code">
reg_ds18b20u_id_msb
reg_uidhr
</td>
<td class="td_code">
DS18B20U_ID_MSB
UIDHR
</td>
</tr>
<tr class="tr_odd">
......@@ -854,13 +854,13 @@ DS18B20U_ID_MSB
REG
</td>
<td >
<A href="#DS18B20U_TEMP">Board temperature</a>
<A href="#TEMPR">TEMPR</a>
</td>
<td class="td_code">
reg_ds18b20u_temp
reg_tempr
</td>
<td class="td_code">
DS18B20U_TEMP
TEMPR
</td>
</tr>
</table>
......@@ -4074,7 +4074,7 @@ reg_lsr_rearfs_i[5:0]
</td>
<td class="td_pblock_right">
reg_mswr_switches_i[31:0]
reg_oswr_switches_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4108,7 +4108,7 @@ reg_mswr_switches_i[31:0]
</td>
<td class="td_pblock_right">
<b>32 least significant bits of DS18B20U:</b>
<b>UIDLR:</b>
</td>
<td class="td_arrow_right">
......@@ -4125,7 +4125,7 @@ reg_mswr_switches_i[31:0]
</td>
<td class="td_pblock_right">
reg_ds18b20u_id_lsb_i[31:0]
reg_uidlr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4159,7 +4159,7 @@ reg_ds18b20u_id_lsb_i[31:0]
</td>
<td class="td_pblock_right">
<b>32 most significant bits of DS18B20U:</b>
<b>UIDHR:</b>
</td>
<td class="td_arrow_right">
......@@ -4176,7 +4176,7 @@ reg_ds18b20u_id_lsb_i[31:0]
</td>
<td class="td_pblock_right">
reg_ds18b20u_id_msb_i[31:0]
reg_uidhr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4210,7 +4210,7 @@ reg_ds18b20u_id_msb_i[31:0]
</td>
<td class="td_pblock_right">
<b>Board temperature:</b>
<b>TEMPR:</b>
</td>
<td class="td_arrow_right">
......@@ -4227,7 +4227,7 @@ reg_ds18b20u_id_msb_i[31:0]
</td>
<td class="td_pblock_right">
reg_ds18b20u_temp_i[15:0]
reg_tempr_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -15016,7 +15016,7 @@ REARFS
</b>[<i>read-only</i>]: Rear panel input failsafe state
<br>High if line is in failsafe mode (e.g., no cable plugged in)<br> Bit 0 -- channel 1<br> Bit 1 -- channel 2<br> etc.
</ul>
<a name="MSWR"></a>
<a name="OSWR"></a>
<h3><a name="sect_3_42">3.42. OSWR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -15024,7 +15024,7 @@ REARFS
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_mswr
reg_oswr
</td>
</tr>
<tr>
......@@ -15040,7 +15040,7 @@ reg_mswr
<b>C prefix: </b>
</td>
<td class="td_code">
MSWR
OSWR
</td>
</tr>
<tr>
......@@ -15277,15 +15277,15 @@ SWITCHES
</b>[<i>read-only</i>]: Switch state
<br>1 -- switch is ON <br> 0 -- switch is OFF
</ul>
<a name="DS18B20U_ID_LSB"></a>
<h3><a name="sect_3_43">3.43. 32 least significant bits of DS18B20U</a></h3>
<a name="UIDLR"></a>
<h3><a name="sect_3_43">3.43. UIDLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ds18b20u_id_lsb
reg_uidlr
</td>
</tr>
<tr>
......@@ -15301,7 +15301,7 @@ reg_ds18b20u_id_lsb
<b>C prefix: </b>
</td>
<td class="td_code">
DS18B20U_ID_LSB
UIDLR
</td>
</tr>
<tr>
......@@ -15345,7 +15345,7 @@ DS18B20U_ID_LSB
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_ID_LSB[31:24]
UIDLR[31:24]
</td>
<td >
......@@ -15399,7 +15399,7 @@ DS18B20U_ID_LSB[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_ID_LSB[23:16]
UIDLR[23:16]
</td>
<td >
......@@ -15453,7 +15453,7 @@ DS18B20U_ID_LSB[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_ID_LSB[15:8]
UIDLR[15:8]
</td>
<td >
......@@ -15507,7 +15507,7 @@ DS18B20U_ID_LSB[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_ID_LSB[7:0]
UIDLR[7:0]
</td>
<td >
......@@ -15534,18 +15534,18 @@ DS18B20U_ID_LSB[7:0]
</table>
<ul>
<li><b>
DS18B20U_ID_LSB
UIDLR
</b>[<i>read-only</i>]: LS bits of 1-wire DS18B20U thermometer ID
</ul>
<a name="DS18B20U_ID_MSB"></a>
<h3><a name="sect_3_44">3.44. 32 most significant bits of DS18B20U</a></h3>
<a name="UIDHR"></a>
<h3><a name="sect_3_44">3.44. UIDHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ds18b20u_id_msb
reg_uidhr
</td>
</tr>
<tr>
......@@ -15561,7 +15561,7 @@ reg_ds18b20u_id_msb
<b>C prefix: </b>
</td>
<td class="td_code">
DS18B20U_ID_MSB
UIDHR
</td>
</tr>
<tr>
......@@ -15605,7 +15605,7 @@ DS18B20U_ID_MSB
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_ID_MSB[31:24]
UIDHR[31:24]
</td>
<td >
......@@ -15659,7 +15659,7 @@ DS18B20U_ID_MSB[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_ID_MSB[23:16]
UIDHR[23:16]
</td>
<td >
......@@ -15713,7 +15713,7 @@ DS18B20U_ID_MSB[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_ID_MSB[15:8]
UIDHR[15:8]
</td>
<td >
......@@ -15767,7 +15767,7 @@ DS18B20U_ID_MSB[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_ID_MSB[7:0]
UIDHR[7:0]
</td>
<td >
......@@ -15794,18 +15794,18 @@ DS18B20U_ID_MSB[7:0]
</table>
<ul>
<li><b>
DS18B20U_ID_MSB
UIDHR
</b>[<i>read-only</i>]: MS bits of 1-wire DS18B20U thermometer ID
</ul>
<a name="DS18B20U_TEMP"></a>
<h3><a name="sect_3_45">3.45. Board temperature</a></h3>
<a name="TEMPR"></a>
<h3><a name="sect_3_45">3.45. TEMPR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ds18b20u_temp
reg_tempr
</td>
</tr>
<tr>
......@@ -15821,7 +15821,7 @@ reg_ds18b20u_temp
<b>C prefix: </b>
</td>
<td class="td_code">
DS18B20U_TEMP
TEMPR
</td>
</tr>
<tr>
......@@ -15834,7 +15834,7 @@ DS18B20U_TEMP
</tr>
</table>
<p>
raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to oC as follows: temp = ((byte1 << 8) | byte0) / 16.0
Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to oC as follows: temp = ((byte1 << 8) | byte0) / 16.0
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -15973,7 +15973,7 @@ raw temperature data from the one wire DS18B20U. The register is 2-bytes long; i
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_TEMP[15:8]
TEMPR[15:8]
</td>
<td >
......@@ -16027,7 +16027,7 @@ DS18B20U_TEMP[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DS18B20U_TEMP[7:0]
TEMPR[7:0]
</td>
<td >
......@@ -16054,8 +16054,9 @@ DS18B20U_TEMP[7:0]
</table>
<ul>
<li><b>
DS18B20U_TEMP
</b>[<i>read-only</i>]: Temperature from DS18B20 thermometer
TEMPR
</b>[<i>read-only</i>]: TEMP
<br>Current on-board temperature
</ul>
......
modules/conv_regs.vhd
View file @ a8c0d688
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : \\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv_regs.vhd
-- Author : auto-generated by wbgen2 from \\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs.wb
-- Created : 10/11/16 16:46:39
-- File : .\conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : 12/20/16 12:38:49
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE \\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -118,8 +118,6 @@ entity conv_regs is
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic; --***added manually
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
......@@ -199,15 +197,13 @@ entity conv_regs is
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
reg_mswr_switches_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
reg_oswr_switches_i : in std_logic_vector(31 downto 0);---added manually
-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: '32 least significant bits of DS18B20U'
reg_ds18b20u_id_lsb_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: '32 most significant bits of DS18B20U'
reg_ds18b20u_id_msb_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Temperature from DS18B20 thermometer' in reg: 'Board temperature'
reg_ds18b20u_temp_i : in std_logic_vector(15 downto 0)
reg_oswr_switches_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR'
reg_uidlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR'
reg_uidhr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR'
reg_tempr_i : in std_logic_vector(15 downto 0)
);
end conv_regs;
......@@ -899,25 +895,25 @@ begin
when "101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_mswr_switches_i;
rddata_reg(31 downto 0) <= reg_oswr_switches_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ds18b20u_id_lsb_i;
rddata_reg(31 downto 0) <= reg_uidlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ds18b20u_id_msb_i;
rddata_reg(31 downto 0) <= reg_uidhr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= reg_ds18b20u_temp_i;
rddata_reg(15 downto 0) <= reg_tempr_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -1038,7 +1034,7 @@ begin
-- Switch state
-- LS bits of 1-wire DS18B20U thermometer ID
-- MS bits of 1-wire DS18B20U thermometer ID
-- Temperature from DS18B20 thermometer
-- TEMP
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/conv_regs.wb
View file @ a8c0d688
......@@ -33,6 +33,8 @@
-- Denia Bouhired Added separate pulse counters for TTL and BLO pulses
-- 11-10-2016 Denia Bouhired Added thermometer registers one 16 bit for temperature read out
-- 2 for LSBs and MSBs of 64-bit ID
-- 20-12-2016 Denia Bouhired Small modification to file in order to match that of wr-n-therm branch from
-- Theodor Stana
--==============================================================================
-- TODO: -
--==============================================================================
......@@ -670,7 +672,7 @@ peripheral {
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
-- prefix = "tai";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
......@@ -904,7 +906,7 @@ peripheral {
reg {
name = "OSWR";
description = "Other Switch Register";
prefix = "mswr";
prefix = "oswr";
field {
name = "Switch state";
description = "1 -- switch is ON \
......@@ -919,9 +921,9 @@ peripheral {
-- 32 LS Bits of 64 bit ID of 1-Wire thermometer
reg {
name = "32 least significant bits of DS18B20U";
name = "UIDLR";
description = "32 LS bits of 1-wire thermometer ID";
prefix = "DS18B20U_ID_LSB";
prefix = "uidlr";
field {
name = "LS bits of 1-wire DS18B20U thermometer ID";
type = SLV;
......@@ -933,9 +935,9 @@ peripheral {
-- 32 MS Bits of 64 bit ID of 1-Wire thermometer
reg {
name = "32 most significant bits of DS18B20U";
name = "UIDHR";
description = "32 MS bits of 1-wire thermometer ID";
prefix = "DS18B20U_ID_MSB";
prefix = "uidhr";
field {
name = "MS bits of 1-wire DS18B20U thermometer ID";
type = SLV;
......@@ -947,11 +949,13 @@ peripheral {
-- 16 bit temperature
reg {
name = "Board temperature";
description = "raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to oC as follows: temp = ((byte1 << 8) | byte0) / 16.0";
prefix = "DS18B20U_temp";
name = "TEMPR";
description = "Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to oC as follows: temp = ((byte1 << 8) | byte0) / 16.0";
prefix = "tempr";
field {
name = "Temperature from DS18B20 thermometer";
name = "TEMP";
description = "Current on-board temperature";
type = SLV;
size = 16;
access_bus = READ_ONLY;
......
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