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level-conversion
conv-common-gw
Commits
f034639f
Commit
f034639f
authored
Aug 05, 2016
by
Denia Bouhired-Ferrag
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Added inv ttl i/o and inv ttl LEDs
parent
3ae0cfc2
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2 changed files
with
83 additions
and
4 deletions
+83
-4
conv_common_gw.vhd
top/conv_common_gw.vhd
+78
-3
conv_common_gw_pkg.vhd
top/conv_common_gw_pkg.vhd
+5
-1
No files found.
top/conv_common_gw.vhd
View file @
f034639f
...
...
@@ -63,6 +63,8 @@ entity conv_common_gw is
(
-- Number of repeater channels
g_nr_chans
:
integer
:
=
6
;
-- DB Number of inverter channels
g_nr_inv_chans
:
integer
:
=
4
;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
...
...
@@ -119,10 +121,19 @@ entity conv_common_gw is
-- Pulse inputs
pulse_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
pulse_o
:
out
std_logic_vector
(
g_nr_chans
-1
downto
0
);
-- DB Inverted pulse I/O
inv_pulse_i_n
:
in
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
inv_pulse_o
:
out
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
-- Channel leds
-- 26 ms active-high pulse on pulse_o rising edge
led_pulse_o
:
out
std_logic_vector
(
g_nr_chans
-1
downto
0
);
-- DB Inverted channel leds
-- 26 ms active-high pulse on pulse_o rising edge
led_inv_pulse_o
:
out
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
--DB *
-- I2C interface
scl_i
:
in
std_logic
;
...
...
@@ -241,7 +252,11 @@ architecture arch of conv_common_gw is
--============================================================================
-- Max. channel count of c_max_nr_chans enforced here:
type
t_pulse_led_cnt
is
array
(
c_max_nr_chans
-1
downto
0
)
of
unsigned
(
18
downto
0
);
of
unsigned
(
8
downto
0
);
type
t_inv_pulse_led_cnt
is
array
(
g_nr_inv_chans
-1
downto
0
)
-- DB *
of
unsigned
(
8
downto
0
);
-- DB *
type
t_pulse_cnt
is
array
(
c_max_nr_chans
-1
downto
0
)
of
unsigned
(
31
downto
0
);
type
t_ch_pcr
is
array
(
c_max_nr_chans
-1
downto
0
)
...
...
@@ -273,6 +288,9 @@ architecture arch of conv_common_gw is
signal
pulse_outp
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp_d0
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp_redge_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
inv_pulse_outp
:
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
--DB *
signal
inv_pulse_outp_d0
:
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
--DB *
signal
inv_pulse_outp_fedge_p
:
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
--DB *
signal
pmisse_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
-- Output enable signals
...
...
@@ -324,6 +342,8 @@ architecture arch of conv_common_gw is
-- LED signals
signal
led_pulse
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
led_pulse_cnt
:
t_pulse_led_cnt
;
signal
led_inv_pulse
:
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
-- DB *
signal
led_inv_pulse_cnt
:
t_pulse_led_cnt
;
-- DB *
signal
led_i2c
:
std_logic
;
signal
led_i2c_clkdiv
:
unsigned
(
18
downto
0
);
signal
led_i2c_cnt
:
unsigned
(
2
downto
0
);
...
...
@@ -401,7 +421,7 @@ begin
generic
map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time
=>
2
*
(
10
**
6
)
g_reset_time
=>
2
*
(
10
**
4
)
-- DB change back to 6
)
port
map
(
...
...
@@ -630,6 +650,60 @@ end generate gen_pulse_cnt;
end
generate
gen_pulse_chan_logic
;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
---Denia Bouhired 02\08\2016
---Move inv channel reflection to common gw module.
--Add 4 input and 4 output ports for signals
--Add 4 output ports for pulse LEDs
----------------------------------------
--DB modif, copied from rs485 top module
-- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input
-- LED flash length: 26 ms
gen_inv_ttl_leds
:
for
i
in
0
to
3
generate
-- INV-TTL outputs
inv_pulse_outp
(
i
)
<=
inv_pulse_i_n
(
i
);
inv_pulse_o
(
i
)
<=
inv_pulse_outp
(
i
);
p_inv_pulse_led
:
process
(
clk_20_i
)
is
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
inv_pulse_outp_d0
(
i
)
<=
'0'
;
inv_pulse_outp_fedge_p
(
i
)
<=
'0'
;
led_inv_pulse_cnt
(
i
)
<=
(
others
=>
'0'
);
led_inv_pulse
(
i
)
<=
'0'
;
else
inv_pulse_outp_d0
(
i
)
<=
inv_pulse_outp
(
i
);
inv_pulse_outp_fedge_p
(
i
)
<=
(
not
inv_pulse_outp
(
i
))
and
inv_pulse_outp_d0
(
i
);
case
led_inv_pulse
(
i
)
is
when
'0'
=>
if
(
inv_pulse_outp_fedge_p
(
i
)
=
'1'
)
then
led_inv_pulse
(
i
)
<=
'1'
;
end
if
;
when
'1'
=>
led_inv_pulse_cnt
(
i
)
<=
led_inv_pulse_cnt
(
i
)
+
1
;
if
(
led_inv_pulse_cnt
(
i
)
=
(
led_inv_pulse_cnt
(
i
)
'range
=>
'1'
))
then
led_inv_pulse
(
i
)
<=
'0'
;
end
if
;
when
others
=>
led_inv_pulse
(
i
)
<=
'0'
;
end
case
;
end
if
;
end
if
;
end
process
p_inv_pulse_led
;
end
generate
gen_inv_ttl_leds
;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
...
...
@@ -721,6 +795,7 @@ end generate gen_pulse_timetag;
-- Channel output assignments
pulse_o
<=
pulse_outp
;
led_pulse_o
<=
led_pulse
;
led_inv_pulse_o
<=
led_inv_pulse
;
-- DB *
--============================================================================
-- I2C bridge logic
...
...
top/conv_common_gw_pkg.vhd
View file @
f034639f
...
...
@@ -64,7 +64,7 @@ package conv_common_gw_pkg is
(
-- Number of repeater channels
g_nr_chans
:
integer
:
=
6
;
g_nr_inv_chans
:
integer
:
=
4
;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
g_board_id
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -123,7 +123,11 @@ package conv_common_gw_pkg is
-- Channel leds
-- 26 ms active-high pulse on pulse_o rising edge
inv_pulse_i_n
:
in
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
inv_pulse_o
:
out
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
led_pulse_o
:
out
std_logic_vector
(
g_nr_chans
-1
downto
0
);
led_inv_pulse_o
:
out
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
--DB *
-- I2C interface
scl_i
:
in
std_logic
;
...
...
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