Bug fix: counter for pps signal actually requires +ve logic reset signal

fa08e685 · Denia Bouhired-Ferrag · dae9b236 · fa08e685
Commit fa08e685 authored Dec 21, 2016 by Denia Bouhired-Ferrag
Hide whitespace changes
Inline Side-by-side

Showing with 4 additions and 3 deletions

conv_common_gw.vhd top/conv_common_gw.vhd +4 -3

No files found.
--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -300,6 +300,7 @@ architecture arch of conv_common_gw is
  signal clk_125             : std_logic;
  signal rst_125_n           : std_logic;
  signal rst_20_n            : std_logic;
+  signal rst_20            : std_logic;
  signal rst_ext             : std_logic;

  -- Pulse logic signals
@@ -1436,21 +1437,21 @@ end generate gen_latest_timestamp_unused_chans;
 	 );

 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- pps generator based on the 100 MHz clk
+  -- pps generator based on the 20 MHz clk
  cmp_pps_gen: wf_decr_counter
  generic map(
  g_counter_lgth   => 25
  )
  port map
    (uclk_i            => clk_20_i,
-     counter_rst_i     => rst_20_n,
+     counter_rst_i     => rst_20,
     counter_decr_i    => '1',
     counter_load_i    => pps_load_p,
     counter_top_i     => "1001100010010110100000000", -- 20'000'000
     counter_is_zero_o => pps_is_zero);
  --  --  --  --  --  --  --  --  --  --  --
  pps_load_p <= pps_is_zero; -- looping
-
+  rst_20 <= not rst_20_n;
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- registering of the read values
  reg_reading: process(clk_20_i)