Skip to content

C
conv-common-gw
Commit aa7b1aff authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
Browse files
Options

Added new registers to count TTL pulses and Blocking pulses separately for each… 

Added new registers to count TTL pulses and Blocking pulses separately for each channel, instead of counting the OR of the two
parent 3c3a48f5
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 469 additions and 182 deletions
modules/conv_regs.vhd
View file @ aa7b1aff
This diff is collapsed.
modules/conv_regs.wb
View file @ aa7b1aff
......@@ -186,13 +186,13 @@ peripheral {
};
};
-- Pulse counter registers, R/W access from SysMon
-- Pulse counter registers for TTL pulses, R/W access from SysMon
reg {
name = "CH1PCR";
description = "Channel 1 Pulse Counter Register";
prefix = "ch1pcr";
name = "CH1TTLPCR";
description = "Channel 1 Pulse Counter Register for TTL pulses";
prefix = "ch1ttlpcr";
field {
name = "Pulse counter value";
name = "TTL pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -202,11 +202,11 @@ peripheral {
};
reg {
name = "CH2PCR";
description = "Channel 2 Pulse Counter Register";
prefix = "ch2pcr";
name = "CH2TTLPCR";
description = "Channel 2 Pulse Counter Register for TTL pulses";
prefix = "ch2ttlpcr";
field {
name = "Pulse counter value";
name = "TTL pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -216,11 +216,11 @@ peripheral {
};
reg {
name = "CH3PCR";
description = "Channel 3 Pulse Counter Register";
prefix = "ch3pcr";
name = "CH3TTLPCR";
description = "Channel 3 Pulse Counter Register for TTL pulses";
prefix = "ch3ttlpcr";
field {
name = "Pulse counter value";
name = "TTL pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -230,11 +230,11 @@ peripheral {
};
reg {
name = "CH4PCR";
description = "Channel 4 Pulse Counter Register";
prefix = "ch4pcr";
name = "CH4TTLPCR";
description = "Channel 4 Pulse Counter Register for TTL pulses";
prefix = "ch4ttlpcr";
field {
name = "Pulse counter value";
name = "TTL pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -244,11 +244,11 @@ peripheral {
};
reg {
name = "CH5PCR";
description = "Channel 5 Pulse Counter Register";
prefix = "ch5pcr";
name = "CH5TTLPCR";
description = "Channel 5 Pulse Counter Register for TTL pulses";
prefix = "ch5ttlpcr";
field {
name = "Pulse counter value";
name = "TTL pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -258,11 +258,11 @@ peripheral {
};
reg {
name = "CH6PCR";
description = "Channel 6 Pulse Counter Register";
prefix = "ch6pcr";
name = "CH6TTLPCR";
description = "Channel 6 Pulse Counter Register for TTL pulses";
prefix = "ch6ttlpcr";
field {
name = "Pulse counter value";
name = "TTL pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -271,6 +271,91 @@ peripheral {
};
};
-- Pulse counter registers for blocking pulses, R/W access from SysMon
reg {
name = "CH1BLOPCR";
description = "Channel 1 Pulse Counter Register for BLO pulses";
prefix = "ch1blopcr";
field {
name = "BLO pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH2BLOPCR";
description = "Channel 2 Pulse Counter Register for BLO pulses";
prefix = "ch2blopcr";
field {
name = "BLO pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH3BLOPCR";
description = "Channel 3 Pulse Counter Register for BLO pulses";
prefix = "ch3blopcr";
field {
name = "BLO pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH4BLOPCR";
description = "Channel 4 Pulse Counter Register for BLO pulses";
prefix = "ch4blopcr";
field {
name = "BLO pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH5BLOPCR";
description = "Channel 5 Pulse Counter Register for BLO pulses";
prefix = "ch5blopcr";
field {
name = "BLO pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH6BLOPCR";
description = "Channel 6 Pulse Counter Register for BLO pulses";
prefix = "ch6blopcr";
field {
name = "BLO pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TVLR";
description = "Time Value Low Register";
......@@ -582,7 +667,7 @@ peripheral {
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
prefix = "tai";
-- prefix = "tai";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
......
top/conv_common_gw.vhd
View file @ aa7b1aff
......@@ -87,7 +87,7 @@ entity conv_common_gw is
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
-- Generate logic with pulse counters
-- Generate logic with pulse timetag
g_with_pulse_timetag : boolean := false;
-- Generate logic with manual trigger
......@@ -213,6 +213,7 @@ entity conv_common_gw is
end entity conv_common_gw;
architecture arch of conv_common_gw is
--============================================================================
......@@ -285,6 +286,8 @@ architecture arch of conv_common_gw is
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_ttl_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_blo_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_man : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
......@@ -324,8 +327,14 @@ architecture arch of conv_common_gw is
signal pmisse_bit_rst_ld : std_logic;
signal pmisse_bits_or : std_logic;
signal pulse_cnt : t_pulse_cnt;
signal ch_pcr : t_ch_pcr;
signal ch_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal ttl_pulse_cnt : t_pulse_cnt;
signal blo_pulse_cnt : t_pulse_cnt;
-- signal ch_pcr : t_ch_pcr;
-- signal ch_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal ch_ttl_pcr : t_ch_pcr;
signal ch_ttl_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal ch_blo_pcr : t_ch_pcr;
signal ch_blo_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal mpt_ld : std_logic;
signal mpt : std_logic_vector( 7 downto 0);
signal tvlr : std_logic_vector(31 downto 0);
......@@ -423,7 +432,7 @@ begin
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6)
g_reset_time => 2*(10**4) ---change back to 6
)
port map
(
......@@ -554,7 +563,7 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- to the pulse generator.
--
-- NOTE: glitch-filtered signal is also synced in 20MHz clock domain, but
-- another sync chain here avoids extra logic complication and shoudl have
-- another sync chain here avoids extra logic complication and should have
-- no influence on the correctness of the pulse counter value
cmp_sync_ffs : gc_sync_ffs
port map
......@@ -565,6 +574,14 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
ppulse_o => trig_chan_redge_p(i)
);
-- AND the ttl line with the de-glitched pulse in order to determine
-- source of pulse. If ANDed signal is 1 then TTL source.
trig_chan_ttl_redge_p(i) <= trig_chan_redge_p(i) and line_front_i (i);
-- AND the blo line with the de-glitched pulse in order to determine
-- source of pulse. If ANDed signal is 1 then BLO source.
trig_chan_blo_redge_p(i) <= trig_chan_redge_p(i) and line_rear_i (i);
--------------------------------------------------------------------------------
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
......@@ -574,10 +591,19 @@ gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_cnt(i) <= (others => '0');
elsif (ch_pcr_ld(i) = '1') then
pulse_cnt(i) <= unsigned(ch_pcr(i));
elsif (trig_chan_redge_p(i) = '1') then
pulse_cnt(i) <= pulse_cnt(i) + 1;
ttl_pulse_cnt(i) <= (others => '0');
blo_pulse_cnt(i) <= (others => '0');
elsif (ch_ttl_pcr_ld(i) = '1') then
ttl_pulse_cnt(i) <= unsigned(ch_ttl_pcr(i));
elsif (ch_blo_pcr_ld(i) = '1') then
blo_pulse_cnt(i) <= unsigned(ch_blo_pcr(i));
elsif (trig_chan_redge_p(i) = '1') then
pulse_cnt(i) <= pulse_cnt(i) + 1;
if (trig_chan_ttl_redge_p(i) = '1') then
ttl_pulse_cnt(i) <= ttl_pulse_cnt(i) + 1;
elsif (trig_chan_blo_redge_p(i) = '1') then
blo_pulse_cnt(i) <= blo_pulse_cnt(i) + 1;
end if;
end if;
end if;
end process p_pulse_cnt;
......@@ -586,6 +612,9 @@ gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
-- Connect pulse counter values for unused channels to all zeroes
gen_pulse_cnt_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
ttl_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
blo_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
end generate gen_pulse_cnt_unused_chans;
--------------------------------------------------------------------------------
......@@ -1176,25 +1205,44 @@ end generate gen_latest_timestamp_unused_chans;
reg_cr_mpt_o => mpt,
reg_cr_mpt_wr_o => mpt_ld,
reg_ch1pcr_o => ch_pcr(0),
reg_ch1pcr_i => std_logic_vector(pulse_cnt(0)),
reg_ch1pcr_load_o => ch_pcr_ld(0),
reg_ch2pcr_o => ch_pcr(1),
reg_ch2pcr_i => std_logic_vector(pulse_cnt(1)),
reg_ch2pcr_load_o => ch_pcr_ld(1),
reg_ch3pcr_o => ch_pcr(2),
reg_ch3pcr_i => std_logic_vector(pulse_cnt(2)),
reg_ch3pcr_load_o => ch_pcr_ld(2),
reg_ch4pcr_o => ch_pcr(3),
reg_ch4pcr_i => std_logic_vector(pulse_cnt(3)),
reg_ch4pcr_load_o => ch_pcr_ld(3),
reg_ch5pcr_o => ch_pcr(4),
reg_ch5pcr_i => std_logic_vector(pulse_cnt(4)),
reg_ch5pcr_load_o => ch_pcr_ld(4),
reg_ch6pcr_o => ch_pcr(5),
reg_ch6pcr_i => std_logic_vector(pulse_cnt(5)),
reg_ch6pcr_load_o => ch_pcr_ld(5),
reg_ch1ttlpcr_o => ch_ttl_pcr(0),
reg_ch1ttlpcr_i => std_logic_vector(ttl_pulse_cnt(0)),
reg_ch1ttlpcr_load_o => ch_ttl_pcr_ld(0),
reg_ch2ttlpcr_o => ch_ttl_pcr(1),
reg_ch2ttlpcr_i => std_logic_vector(ttl_pulse_cnt(1)),
reg_ch2ttlpcr_load_o => ch_ttl_pcr_ld(1),
reg_ch3ttlpcr_o => ch_ttl_pcr(2),
reg_ch3ttlpcr_i => std_logic_vector(ttl_pulse_cnt(2)),
reg_ch3ttlpcr_load_o => ch_ttl_pcr_ld(2),
reg_ch4ttlpcr_o => ch_ttl_pcr(3),
reg_ch4ttlpcr_i => std_logic_vector(ttl_pulse_cnt(3)),
reg_ch4ttlpcr_load_o => ch_ttl_pcr_ld(3),
reg_ch5ttlpcr_o => ch_ttl_pcr(4),
reg_ch5ttlpcr_i => std_logic_vector(ttl_pulse_cnt(4)),
reg_ch5ttlpcr_load_o => ch_ttl_pcr_ld(4),
reg_ch6ttlpcr_o => ch_ttl_pcr(5),
reg_ch6ttlpcr_i => std_logic_vector(ttl_pulse_cnt(5)),
reg_ch6ttlpcr_load_o => ch_ttl_pcr_ld(5),
reg_ch1blopcr_o => ch_blo_pcr(0),
reg_ch1blopcr_i => std_logic_vector(blo_pulse_cnt(0)),
reg_ch1blopcr_load_o => ch_blo_pcr_ld(0),
reg_ch2blopcr_o => ch_blo_pcr(1),
reg_ch2blopcr_i => std_logic_vector(blo_pulse_cnt(1)),
reg_ch2blopcr_load_o => ch_blo_pcr_ld(1),
reg_ch3blopcr_o => ch_blo_pcr(2),
reg_ch3blopcr_i => std_logic_vector(blo_pulse_cnt(2)),
reg_ch3blopcr_load_o => ch_blo_pcr_ld(2),
reg_ch4blopcr_o => ch_blo_pcr(3),
reg_ch4blopcr_i => std_logic_vector(blo_pulse_cnt(3)),
reg_ch4blopcr_load_o => ch_blo_pcr_ld(3),
reg_ch5blopcr_o => ch_blo_pcr(4),
reg_ch5blopcr_i => std_logic_vector(blo_pulse_cnt(4)),
reg_ch5blopcr_load_o => ch_blo_pcr_ld(4),
reg_ch6blopcr_o => ch_blo_pcr(5),
reg_ch6blopcr_i => std_logic_vector(blo_pulse_cnt(5)),
reg_ch6blopcr_load_o => ch_blo_pcr_ld(5),
reg_tvlr_o => tvlr,
reg_tvlr_i => tm_tai(31 downto 0),
reg_tvlr_load_o => tvlr_ld,
......
top/conv_common_gw_pkg.vhd
View file @ aa7b1aff
......@@ -319,30 +319,57 @@ package conv_common_gw_pkg is
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH1PCR'
reg_ch1pcr_o : out std_logic_vector(31 downto 0);
reg_ch1pcr_i : in std_logic_vector(31 downto 0);
reg_ch1pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH2PCR'
reg_ch2pcr_o : out std_logic_vector(31 downto 0);
reg_ch2pcr_i : in std_logic_vector(31 downto 0);
reg_ch2pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH3PCR'
reg_ch3pcr_o : out std_logic_vector(31 downto 0);
reg_ch3pcr_i : in std_logic_vector(31 downto 0);
reg_ch3pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH4PCR'
reg_ch4pcr_o : out std_logic_vector(31 downto 0);
reg_ch4pcr_i : in std_logic_vector(31 downto 0);
reg_ch4pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH5PCR'
reg_ch5pcr_o : out std_logic_vector(31 downto 0);
reg_ch5pcr_i : in std_logic_vector(31 downto 0);
reg_ch5pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH6PCR'
reg_ch6pcr_o : out std_logic_vector(31 downto 0);
reg_ch6pcr_i : in std_logic_vector(31 downto 0);
reg_ch6pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL Pulse counter value' in reg: 'CH1TTLPCR'
reg_ch1ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch1ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch1ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL Pulse counter value' in reg: 'CH2TTLPCR'
reg_ch2ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch2ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch2ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL Pulse counter value' in reg: 'CH3TTLPCR'
reg_ch3ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch3ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch3ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL Pulse counter value' in reg: 'CH4TTLPCR'
reg_ch4ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch4ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch4ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL Pulse counter value' in reg: 'CH5TTLPCR'
reg_ch5ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch5ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch5ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL Pulse counter value' in reg: 'CH6TTLPCR'
reg_ch6ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch6ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch6ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO Pulse counter value' in reg: 'CH1BLOPCR'
reg_ch1blopcr_o : out std_logic_vector(31 downto 0);
reg_ch1blopcr_i : in std_logic_vector(31 downto 0);
reg_ch1blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO Pulse counter value' in reg: 'CH2BLOPCR'
reg_ch2blopcr_o : out std_logic_vector(31 downto 0);
reg_ch2blopcr_i : in std_logic_vector(31 downto 0);
reg_ch2blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO Pulse counter value' in reg: 'CH3BLOPCR'
reg_ch3blopcr_o : out std_logic_vector(31 downto 0);
reg_ch3blopcr_i : in std_logic_vector(31 downto 0);
reg_ch3blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO Pulse counter value' in reg: 'CH4BLOPCR'
reg_ch4blopcr_o : out std_logic_vector(31 downto 0);
reg_ch4blopcr_i : in std_logic_vector(31 downto 0);
reg_ch4blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO Pulse counter value' in reg: 'CH5BLOPCR'
reg_ch5blopcr_o : out std_logic_vector(31 downto 0);
reg_ch5blopcr_i : in std_logic_vector(31 downto 0);
reg_ch5blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO Pulse counter value' in reg: 'CH6BLOPCR'
reg_ch6blopcr_o : out std_logic_vector(31 downto 0);
reg_ch6blopcr_i : in std_logic_vector(31 downto 0);
reg_ch6blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment