Commit 87d7325f authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Removed generics port from Instantiation section

Also added link to OHWR Wiki page for project examples in the same section.
parent 92778c1f
title = {{Converter Common Gateware Wiki page on OHWR}},
howpublished = {\url{}}
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
......@@ -136,46 +136,8 @@ the module uses active-high ports, any adaptations to active-low logic must be m
Since there are a lot of ports in the component, listing them all here would be a waste of space.
The reader is referred to the package file or the source file directly, where each port declaration
is commented. Projects where this gateware is already used (e.g., CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr}) can also be a
good source of reference.
The module's generics are listed here for quick reference (Table~\ref{tbl:generics}).
\caption{\label{tbl:generics} Generics of \textit{conv\_common\_gw}}
\begin{tabular}{p{.3\textwidth} p{.7\textwidth}}
\multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Description}} \\
g\_nr\_chans & Number of pulse repetition channels \newline
Max. 6 channels allowed \\
g\_board\_id & Board ID, per the converter board ID page~\cite{board-id} \newline
Connects to BID register \\
g\_gwvers & Current gateware version \newline
Connects to GWVERS field in SR \\
g\_pgen\_fixed\_width & Pulse generator with fixed width at output \newline
\textit{true} -- fixed-width output pulse and pulse rejection after pulse is generated \newline
\textit{false} -- pulse generator is simple pass-through \\
g\_pgen\_pwidth & No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \newline
Pulse width at generator output \newline
Value in number of \textit{clk\_20\_i} cycles \newline
Default: 24 (1.2~${\mu}s$~\cite{blocking}) \newline
Constrained between 20 and 40 \textit{clk\_20\_i} cycles \newline
(1--2~${\mu}s$~\cite{blocking}) \\
g\_pgen\_duty\_cycle\_div & No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \newline
Divider ratio of pulse rejection mechanism \newline
Output max. freq. 1/g\_pgen\_duty\_cycle\_div \\
g\_pgen\_gf\_len & Pulse generation mechanism glitch filter length in number of \textit{clk\_20\_i} cycles \\
g\_bicolor\_led\_columns & Number of columns for bicolor LED controller \\
g\_bicolor\_led\_lines & Number of lines for bicolor LED controller \\
is commented. Projects where this gateware is already used can also be a good source of
reference (see the \textit{conv-common-gw} project Wiki page~\cite{conv-common-gw-wiki}).
% SEC: Top-level diagram
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