platform/xilinx: don't constrain clock frequencies in the GTHE4 XDC file, they are already set in the top level XDC

modules/wr_streamers: make DBG_WORD optional (generic parameter). Remove MARK_DEBUG attributes to facilitate timing closure

- REQUIRES V5 DEV BRANCH WRPC-SW
- syscon diag registers (read-write) are now remapped at offset (periph + 0x900)
- user diag registers are at the previous address (periph + 0x800), keeping the legacy layout
- the new scheme uses much less FF/LUT resources and allows adding arbitrary diagnostics without affecting the SYSCON layout or HDL modifications

- generate common (ch0 & ch1) reset synched with ch01_ref_clk_i
- ch0_gtp_reset and ch1_gtp_reset were not driven
- and some more cleaing

wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address space. Default is 128kB (legacy)