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White Rabbit core collection
Commit 983726db authored by Tristan Gingold's avatar Tristan Gingold
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Merge remote-tracking branch 'origin/diot-sb' into wrpc-v5

parents 57444e79 6e64fab1
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    board/Manifest.py
    View file @ 983726db
    try:
    if board in ["spec", "svec", "vfchd", "clbv2", "clbv3", "clbv4", "pxie-fmc", "common"]:
    if board in ["spec", "svec", "vfchd", "clbv2", "clbv3", "clbv4", "pxie-fmc", "diot-sb", "common"]:
    modules = {"local" : [ board ] }
    except NameError:
    pass
    board/common/xwrc_board_common.vhd
    View file @ 983726db
    ......@@ -496,86 +496,86 @@ begin -- architecture struct
    gen_wr_streamers : if (g_fabric_iface = STREAMERS) generate
    cmp_xwr_streamers : xwr_streamers
    generic map (
    g_streamers_op_mode => g_streamers_op_mode,
    g_tx_streamer_params => g_tx_streamer_params,
    g_rx_streamer_params => g_rx_streamer_params,
    g_simulation => g_simulation,
    g_clk_ref_rate => f_pick_clk_ref_rate(g_pcs_16bit))
    port map (
    clk_sys_i => clk_sys_i,
    rst_n_i => rst_n_i,
    src_i => wrf_snk_out,
    src_o => wrf_snk_in,
    snk_i => wrf_src_out,
    snk_o => wrf_src_in,
    tx_data_i => wrs_tx_data_i,
    tx_valid_i => wrs_tx_valid_i,
    tx_dreq_o => wrs_tx_dreq_o,
    tx_last_p1_i => wrs_tx_last_i,
    tx_flush_p1_i => wrs_tx_flush_i,
    rx_first_p1_o => wrs_rx_first_o,
    rx_last_p1_o => wrs_rx_last_o,
    rx_data_o => wrs_rx_data_o,
    rx_valid_o => wrs_rx_valid_o,
    rx_dreq_i => wrs_rx_dreq_i,
    clk_ref_i => clk_ref_i,
    tm_time_valid_i => tm_time_valid,
    tm_tai_i => tm_tai,
    tm_cycles_i => tm_cycles,
    link_ok_i => link_ok,
    wb_slave_i => aux_master_out,
    wb_slave_o => aux_master_in,
    snmp_array_o => aux_diag_in(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0),
    snmp_array_i => aux_diag_out(c_WR_STREAMERS_ARR_SIZE_IN-1 downto 0),
    tx_streamer_cfg_i=> wrs_tx_cfg_i,
    rx_streamer_cfg_i=> wrs_rx_cfg_i);
    -- unused output ports
    wrf_src_o <= c_dummy_snk_in;
    wrf_snk_o <= c_dummy_src_in;
    aux_master_o <= cc_dummy_master_out;
    wb_eth_master_o <= cc_dummy_master_out;
    aux_diag_in(c_diag_ro_size-1 downto c_WR_STREAMERS_ARR_SIZE_OUT) <= aux_diag_i;
    aux_diag_o <= aux_diag_out(c_diag_rw_size-1 downto c_WR_STREAMERS_ARR_SIZE_IN);
    --GD cmp_xwr_streamers : xwr_streamers
    --GD generic map (
    --GD g_streamers_op_mode => g_streamers_op_mode,
    --GD g_tx_streamer_params => g_tx_streamer_params,
    --GD g_rx_streamer_params => g_rx_streamer_params,
    --GD g_simulation => g_simulation,
    --GD g_clk_ref_rate => f_pick_clk_ref_rate(g_pcs_16bit))
    --GD port map (
    --GD clk_sys_i => clk_sys_i,
    --GD rst_n_i => rst_n_i,
    --GD src_i => wrf_snk_out,
    --GD src_o => wrf_snk_in,
    --GD snk_i => wrf_src_out,
    --GD snk_o => wrf_src_in,
    --GD tx_data_i => wrs_tx_data_i,
    --GD tx_valid_i => wrs_tx_valid_i,
    --GD tx_dreq_o => wrs_tx_dreq_o,
    --GD tx_last_p1_i => wrs_tx_last_i,
    --GD tx_flush_p1_i => wrs_tx_flush_i,
    --GD rx_first_p1_o => wrs_rx_first_o,
    --GD rx_last_p1_o => wrs_rx_last_o,
    --GD rx_data_o => wrs_rx_data_o,
    --GD rx_valid_o => wrs_rx_valid_o,
    --GD rx_dreq_i => wrs_rx_dreq_i,
    --GD clk_ref_i => clk_ref_i,
    --GD tm_time_valid_i => tm_time_valid,
    --GD tm_tai_i => tm_tai,
    --GD tm_cycles_i => tm_cycles,
    --GD link_ok_i => link_ok,
    --GD wb_slave_i => aux_master_out,
    --GD wb_slave_o => aux_master_in,
    --GD snmp_array_o => aux_diag_in(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0),
    --GD snmp_array_i => aux_diag_out(c_WR_STREAMERS_ARR_SIZE_IN-1 downto 0),
    --GD tx_streamer_cfg_i=> wrs_tx_cfg_i,
    --GD rx_streamer_cfg_i=> wrs_rx_cfg_i);
    --GD
    --GD -- unused output ports
    --GD wrf_src_o <= c_dummy_snk_in;
    --GD wrf_snk_o <= c_dummy_src_in;
    --GD
    --GD aux_master_o <= cc_dummy_master_out;
    --GD wb_eth_master_o <= cc_dummy_master_out;
    --GD
    --GD aux_diag_in(c_diag_ro_size-1 downto c_WR_STREAMERS_ARR_SIZE_OUT) <= aux_diag_i;
    --GD aux_diag_o <= aux_diag_out(c_diag_rw_size-1 downto c_WR_STREAMERS_ARR_SIZE_IN);
    end generate gen_wr_streamers;
    gen_etherbone : if (g_fabric_iface = ETHERBONE) generate
    cmp_eb_ethernet_slave : eb_ethernet_slave
    generic map (
    g_sdb_address => x"0000000000030000")
    port map (
    clk_i => clk_sys_i,
    nRst_i => aux_rst_n,
    src_o => wrf_snk_in,
    src_i => wrf_snk_out,
    snk_o => wrf_src_in,
    snk_i => wrf_src_out,
    cfg_slave_o => aux_master_in,
    cfg_slave_i => aux_master_out,
    master_o => wb_eth_master_o,
    master_i => wb_eth_master_i);
    -- unused output ports
    wrf_src_o <= c_dummy_snk_in;
    wrf_snk_o <= c_dummy_src_in;
    wrs_tx_dreq_o <= '0';
    wrs_rx_first_o <= '0';
    wrs_rx_last_o <= '0';
    wrs_rx_valid_o <= '0';
    wrs_rx_data_o <= (others => '0');
    aux_master_o <= cc_dummy_master_out;
    -- unused inputs to WR PTP core
    aux_diag_in <= aux_diag_i;
    aux_diag_o <= aux_diag_out;
    --GD cmp_eb_ethernet_slave : eb_ethernet_slave
    --GD generic map (
    --GD g_sdb_address => x"0000000000030000")
    --GD port map (
    --GD clk_i => clk_sys_i,
    --GD nRst_i => aux_rst_n,
    --GD src_o => wrf_snk_in,
    --GD src_i => wrf_snk_out,
    --GD snk_o => wrf_src_in,
    --GD snk_i => wrf_src_out,
    --GD cfg_slave_o => aux_master_in,
    --GD cfg_slave_i => aux_master_out,
    --GD master_o => wb_eth_master_o,
    --GD master_i => wb_eth_master_i);
    --GD
    --GD -- unused output ports
    --GD wrf_src_o <= c_dummy_snk_in;
    --GD wrf_snk_o <= c_dummy_src_in;
    --GD
    --GD wrs_tx_dreq_o <= '0';
    --GD wrs_rx_first_o <= '0';
    --GD wrs_rx_last_o <= '0';
    --GD wrs_rx_valid_o <= '0';
    --GD wrs_rx_data_o <= (others => '0');
    --GD
    --GD aux_master_o <= cc_dummy_master_out;
    --GD
    --GD -- unused inputs to WR PTP core
    --GD aux_diag_in <= aux_diag_i;
    --GD aux_diag_o <= aux_diag_out;
    end generate gen_etherbone;
    ......
    board/diot-sb/Manifest.py 0 → 100644
    View file @ 983726db
    files = [
    "wrc_board_diot_simple.vhd",
    ]
    modules = {
    "local" : [
    "../common",
    ]
    }
    board/diot-sb/wrc_board_diot_simple.vhd 0 → 100644
    View file @ 983726db
    This diff is collapsed.
    general-cores @ b75fe3d5
    Subproject commit 347e0de1e0d91834d298a146569530b71adeb33a
    Subproject commit b75fe3d51950c53dd29c980f4407afd00703ccc4
    modules/wr_mini_nic/minic_wb_slave.vhd
    View file @ 983726db
    ......@@ -3,7 +3,7 @@
    ---------------------------------------------------------------------------------------
    -- File : minic_wb_slave.vhd
    -- Author : auto-generated by wbgen2 from mini_nic.wb
    -- Created : Wed Aug 16 22:41:57 2017
    -- Created : Tue Oct 13 09:42:36 2020
    -- Standard : VHDL'87
    ---------------------------------------------------------------------------------------
    -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
    ......@@ -30,6 +30,8 @@ entity minic_wb_slave is
    wb_stb_i : in std_logic;
    wb_we_i : in std_logic;
    wb_ack_o : out std_logic;
    wb_err_o : out std_logic;
    wb_rty_o : out std_logic;
    wb_stall_o : out std_logic;
    wb_int_o : out std_logic;
    tx_ts_read_ack_o : out std_logic;
    ......@@ -65,8 +67,13 @@ signal irq_inputs_vector_int : std_logic_vector(2 downto 0);
    signal ack_sreg : std_logic_vector(9 downto 0);
    signal rddata_reg : std_logic_vector(31 downto 0);
    signal wrdata_reg : std_logic_vector(31 downto 0);
    signal bwsel_reg : std_logic_vector(3 downto 0);
    signal rwaddr_reg : std_logic_vector(4 downto 0);
    signal ack_in_progress : std_logic ;
    signal wr_int : std_logic ;
    signal rd_int : std_logic ;
    signal allones : std_logic_vector(31 downto 0);
    signal allzeros : std_logic_vector(31 downto 0);
    begin
    -- Some internal signals assignments
    ......@@ -597,6 +604,8 @@ begin
    irq_inputs_vector_int(2) <= irq_txts_i;
    rwaddr_reg <= wb_adr_i;
    wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
    wb_err_o <= '0';
    wb_rty_o <= '0';
    -- ACK signal generation. Just pass the LSB of ACK counter.
    wb_ack_o <= ack_sreg(0);
    end syn;
    modules/wr_mini_nic/minic_wbgen2_pkg.vhd
    View file @ 983726db
    ......@@ -3,7 +3,7 @@
    ---------------------------------------------------------------------------------------
    -- File : minic_wbgen2_pkg.vhd
    -- Author : auto-generated by wbgen2 from mini_nic.wb
    -- Created : Wed Aug 16 22:41:57 2017
    -- Created : Tue Oct 13 09:42:36 2020
    -- Standard : VHDL'87
    ---------------------------------------------------------------------------------------
    -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
    ......@@ -109,7 +109,7 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
    variable tmp: std_logic_vector(x'length-1 downto 0);
    begin
    for i in 0 to x'length-1 loop
    if x(i) = '1' then
    if(x(i) = '1') then
    tmp(i):= '1';
    else
    tmp(i):= '0';
    ......
    modules/wrc_core/wrc_diags_pkg.vhd
    View file @ 983726db
    ......@@ -3,7 +3,7 @@
    ---------------------------------------------------------------------------------------
    -- File : wrc_diags_pkg.vhd
    -- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
    -- Created : Mon Nov 27 13:37:56 2017
    -- Created : Mon Nov 2 16:06:06 2020
    -- Version : 0x00000001
    -- Standard : VHDL'87
    ---------------------------------------------------------------------------------------
    ......@@ -97,7 +97,7 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
    variable tmp: std_logic_vector(x'length-1 downto 0);
    begin
    for i in 0 to x'length-1 loop
    if x(i) = '1' then
    if(x(i) = '1') then
    tmp(i):= '1';
    else
    tmp(i):= '0';
    ......
    modules/wrc_core/wrc_diags_wb.vhd
    View file @ 983726db
    ......@@ -3,7 +3,7 @@
    ---------------------------------------------------------------------------------------
    -- File : wrc_diags_wb.vhd
    -- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
    -- Created : Mon Nov 27 13:37:56 2017
    -- Created : Mon Nov 2 16:06:06 2020
    -- Version : 0x00000001
    -- Standard : VHDL'87
    ---------------------------------------------------------------------------------------
    ......@@ -30,6 +30,8 @@ entity wrc_diags_wb is
    wb_stb_i : in std_logic;
    wb_we_i : in std_logic;
    wb_ack_o : out std_logic;
    wb_err_o : out std_logic;
    wb_rty_o : out std_logic;
    wb_stall_o : out std_logic;
    regs_i : in t_wrc_diags_in_registers;
    regs_o : out t_wrc_diags_out_registers
    ......@@ -43,8 +45,13 @@ signal wrc_diags_ctrl_data_snapshot_int : std_logic ;
    signal ack_sreg : std_logic_vector(9 downto 0);
    signal rddata_reg : std_logic_vector(31 downto 0);
    signal wrdata_reg : std_logic_vector(31 downto 0);
    signal bwsel_reg : std_logic_vector(3 downto 0);
    signal rwaddr_reg : std_logic_vector(4 downto 0);
    signal ack_in_progress : std_logic ;
    signal wr_int : std_logic ;
    signal rd_int : std_logic ;
    signal allones : std_logic_vector(31 downto 0);
    signal allzeros : std_logic_vector(31 downto 0);
    begin
    -- Some internal signals assignments
    ......@@ -371,6 +378,8 @@ begin
    -- Data
    rwaddr_reg <= wb_adr_i;
    wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
    wb_err_o <= '0';
    wb_rty_o <= '0';
    -- ACK signal generation. Just pass the LSB of ACK counter.
    wb_ack_o <= ack_sreg(0);
    end syn;
    platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd
    View file @ 983726db
    ......@@ -75,6 +75,76 @@ end wr_gthe4_phy_family7_xilinx_ip;
    architecture rtl of wr_gthe4_phy_family7_xilinx_ip is
    component gtwizard_ultrascale_2 is
    port (
    gthrxn_in : in std_logic;
    gthrxp_in : in std_logic;
    gthtxn_out : out std_logic;
    gthtxp_out : out std_logic;
    gtwiz_userclk_tx_reset_in : in std_logic_vector(0 downto 0);
    gtwiz_userclk_tx_usrclk_out : out std_logic_vector(0 downto 0);
    gtwiz_userclk_tx_usrclk2_out : out std_logic_vector(0 downto 0);
    gtwiz_userclk_tx_active_out : out std_logic_vector(0 downto 0);
    gtwiz_userclk_rx_reset_in : in std_logic_vector(0 downto 0);
    gtwiz_userclk_rx_usrclk_out : out std_logic_vector(0 downto 0);
    gtwiz_userclk_rx_usrclk2_out : out std_logic_vector(0 downto 0);
    gtwiz_userclk_rx_active_out : out std_logic_vector(0 downto 0);
    gtwiz_buffbypass_tx_reset_in : in std_logic_vector(0 downto 0);
    gtwiz_buffbypass_tx_start_user_in : in std_logic_vector(0 downto 0);
    gtwiz_buffbypass_tx_done_out : out std_logic_vector(0 downto 0);
    gtwiz_buffbypass_tx_error_out : out std_logic_vector(0 downto 0);
    gtwiz_buffbypass_rx_reset_in : in std_logic_vector(0 downto 0);
    gtwiz_buffbypass_rx_start_user_in : in std_logic_vector(0 downto 0);
    gtwiz_buffbypass_rx_done_out : out std_logic_vector(0 downto 0);
    gtwiz_buffbypass_rx_error_out : out std_logic_vector(0 downto 0);
    drpaddr_in : in std_logic_vector(9 downto 0);
    drpclk_in : in std_logic;
    drpdi_in : in std_logic_vector(15 downto 0);
    drpen_in : in std_logic;
    drpwe_in : in std_logic;
    eyescanreset_in : in std_logic;
    gtrefclk0_in : in std_logic;
    gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0);
    gtwiz_reset_all_in : in std_logic_vector(0 downto 0);
    gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0);
    gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0);
    gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0);
    gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0);
    gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0);
    gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0);
    gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0);
    gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0);
    gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0);
    rx8b10ben_in : in std_logic_vector(0 downto 0);
    rxcommadeten_in : in std_logic_vector(0 downto 0);
    rxmcommaalignen_in : in std_logic_vector(0 downto 0);
    rxpcommaalignen_in : in std_logic_vector(0 downto 0);
    rxslide_in : in std_logic_vector(0 downto 0);
    tx8b10ben_in : in std_logic_vector(0 downto 0);
    txctrl0_in : in std_logic_vector(15 downto 0);
    txctrl1_in : in std_logic_vector(15 downto 0);
    txctrl2_in : in std_logic_vector(7 downto 0);
    rxbyteisaligned_out : out std_logic_vector(0 downto 0);
    rxbyterealign_out : out std_logic;
    rxcommadet_out : out std_logic_vector(0 downto 0);
    rxctrl0_out : out std_logic_vector(15 downto 0);
    rxctrl1_out : out std_logic_vector(15 downto 0);
    rxctrl2_out : out std_logic_vector(7 downto 0);
    rxctrl3_out : out std_logic_vector(7 downto 0);
    rxpmaresetdone_out : out std_logic_vector(0 downto 0);
    txpmaresetdone_out : out std_logic_vector(0 downto 0);
    rxlpmen_in : in std_logic_vector(0 downto 0);
    rxrate_in : in std_logic_vector(2 downto 0);
    txdiffctrl_in : in std_logic_vector(4 downto 0);
    txpostcursor_in : in std_logic_vector(4 downto 0);
    txprecursor_in : in std_logic_vector(4 downto 0)
    );
    end component gtwizard_ultrascale_2;
    signal gtwiz_userclk_tx_reset_in : std_logic;
    -- signal gtwiz_userclk_tx_srcclk_out : std_logic;
    -- signal gtwiz_userclk_tx_usrclk_out : std_logic;
    ......@@ -240,18 +310,19 @@ begin
    gtwiz_reset_all_in <= rst_i;
    U_gtwizard_gthe4 : entity work.gtwizard_ultrascale_2
    -- U_gtwizard_gthe4 : entity work.gtwizard_ultrascale_2
    U_gtwizard_gthe4 : gtwizard_ultrascale_2
    port map (
    gthrxn_in => pad_rxn_i,
    gthrxp_in => pad_rxp_i,
    gthtxn_out => pad_txn_o,
    gthtxp_out => pad_txp_o,
    gtwiz_userclk_tx_reset_in(0) => gtwiz_userclk_tx_reset_in,
    -- gtwiz_userclk_tx_usrclk_out(0) => gtwiz_userclk_tx_usrclk_out,
    -- gtwiz_userclk_tx_usrclk_out(0) => open,
    gtwiz_userclk_tx_usrclk2_out(0) => tx_clk,
    gtwiz_userclk_tx_active_out(0) => gtwiz_userclk_tx_active_out,
    gtwiz_userclk_rx_reset_in(0) => gtwiz_userclk_rx_reset_in,
    -- gtwiz_userclk_rx_usrclk_out(0) => gtwiz_userclk_rx_usrclk_out,
    -- gtwiz_userclk_rx_usrclk_out(0) => open,
    gtwiz_userclk_rx_usrclk2_out(0) => rx_clk,
    gtwiz_userclk_rx_active_out(0) => gtwiz_userclk_rx_active_out,
    gtwiz_buffbypass_tx_reset_in(0) => gtwiz_buffbypass_tx_reset_in,
    ......
    platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
    View file @ 983726db
    ......@@ -69,7 +69,7 @@ use UNISIM.VCOMPONENTS.ALL;
    --***************************** Entity Declaration ****************************
    entity whiterabbit_gtxe2_channel_wrapper_GT is
    entity whiterabbit_gtxe2_channel_wrapper_gt is
    generic
    (
    -- Simulation attributes
    ......@@ -162,9 +162,9 @@ port
    );
    end whiterabbit_gtxe2_channel_wrapper_GT;
    end whiterabbit_gtxe2_channel_wrapper_gt;
    architecture RTL of whiterabbit_gtxe2_channel_wrapper_GT is
    architecture RTL of whiterabbit_gtxe2_channel_wrapper_gt is
    --**************************** Signal Declarations ****************************
    ......
    platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
    View file @ 983726db
    ......@@ -118,7 +118,7 @@ end wr_gtx_phy_family7;
    architecture rtl of wr_gtx_phy_family7 is
    component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT is
    component whiterabbit_gtxe2_channel_wrapper_gt is
    generic
    (
    -- Simulation attributes
    ......@@ -208,7 +208,7 @@ architecture rtl of wr_gtx_phy_family7 is
    ------------------ Transmit Ports - pattern Generator Ports ----------------
    TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
    );
    end component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT;
    end component whiterabbit_gtxe2_channel_wrapper_gt;
    component BUFG
    port (
    ......@@ -325,11 +325,14 @@ begin -- rtl
    tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
    tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
    U_GTX_INST : WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT
    U_GTX_INST : whiterabbit_gtxe2_channel_wrapper_gt
    generic map
    (
    -- Simulation attributes
    GT_SIM_GTRESET_SPEEDUP => "TRUE" -- Set to "true" to speed up sim reset
    GT_SIM_GTRESET_SPEEDUP => "TRUE", -- Set to "true" to speed up sim reset
    RX_DFE_KL_CFG2_IN => X"3010D90C",
    PMA_RSV_IN => X"00018480",
    PCS_RSVD_ATTR_IN => X"000000000000"
    )
    port map
    (
    ......
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v
    View file @ 983726db
    ......@@ -1150,7 +1150,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
    for (cm = 0; cm < `gtwizard_ultrascale_2_gtwizard_gthe4_MAX_NUM_COMMONS; cm = cm + 1) begin : gen_common_container
    if (P_COMMON_ENABLE[cm] == 1'b1) begin : gen_enabled_common
    gtwizard_ultrascale_2_gthe4_common_wrapper gthe4_common_wrapper_inst (
    /* gtwizard_ultrascale_2_gthe4_common_wrapper gthe4_common_wrapper_inst (
    .GTHE4_COMMON_BGBYPASSB (bgbypassb_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]),
    .GTHE4_COMMON_BGMONITORENB (bgmonitorenb_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]),
    .GTHE4_COMMON_BGPDB (bgpdb_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]),
    ......@@ -1238,7 +1238,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
    .GTHE4_COMMON_SDM1TESTDATA (sdm1testdata_int [f_ub_cm(15,(4*cm)+3) : f_lb_cm(15,4*cm)]),
    .GTHE4_COMMON_TCONGPO (tcongpo_int [f_ub_cm(10,(4*cm)+3) : f_lb_cm(10,4*cm)]),
    .GTHE4_COMMON_TCONRSVDOUT0 (tconrsvdout0_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)])
    );
    );*/
    end
    end
    ......@@ -2595,80 +2595,80 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
    assign drpen_ch_int = drpen_int;
    assign drpwe_ch_int = drpwe_int;
    end
    if (0) begin : gen_cpll_cal_gtye4
    gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal #(
    .C_SIM_CPLL_CAL_BYPASS(
    //pragma translate_off
    C_SIM_CPLL_CAL_BYPASS ||
    //pragma translate_on
    1'b0
    ),
    .C_PCIE_ENABLE(C_PCIE_ENABLE),
    .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
    .C_RX_PLL_TYPE(C_RX_PLL_TYPE),
    .C_TX_PLL_TYPE(C_TX_PLL_TYPE),
    .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ)
    ) gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst (
    .TXOUTCLK_PERIOD_IN (18'b0),
    .WAIT_DEASSERT_CPLLPD_IN (16'b0),
    .CNT_TOL_IN (18'b0),
    .FREQ_COUNT_WINDOW_IN (16'b0),
    .RESET_IN (1'b0),
    .CLK_IN (1'b0),
    .DRPRST_IN (1'b0),
    .USER_TXOUTCLK_BUFG_CE_IN (1'b0),
    .USER_TXOUTCLK_BUFG_CLR_IN (1'b0),
    .USER_TXPROGDIVRESET_IN (1'b0),
    .GTYE4_RXOUTCLK_IN (1'b0),
    .GTYE4_RXPMARESETDONE_IN (1'b0),
    .GTYE4_RXPRGDIVRESETDONE_IN (1'b0),
    .USER_GTRXRESET_IN (1'b0),
    .USER_RXCDRHOLD_IN (1'b0),
    .USER_RXOUTCLK_BUFG_CE_IN (1'b0),
    .USER_RXOUTCLK_BUFG_CLR_IN (1'b0),
    .USER_RXPMARESET_IN (1'b0),
    .USER_RXPROGDIVRESET_IN (1'b0),
    .USER_RXPLLCLKSEL (2'b00),
    .USER_TXPLLCLKSEL (2'b00),
    .USER_RXOUTCLKSEL_IN (3'b010),
    .GTYE4_GTRXRESET_OUT (),
    .GTYE4_RXCDRHOLD_OUT (),
    .GTYE4_RXPMARESET_OUT (),
    .GTYE4_RXPROGDIVRESET_OUT (),
    .USER_RXPMARESETDONE_OUT (),
    .USER_RXPRGDIVRESETDONE_OUT (),
    .GTYE4_RXOUTCLKSEL_OUT (),
    .USER_TXPRGDIVRESETDONE_OUT (),
    .USER_TXOUTCLKSEL_IN (3'b0),
    .USER_CPLLLOCK_OUT (),
    .USER_CHANNEL_DRPADDR_IN (9'b0),
    .USER_CHANNEL_DRPDI_IN (16'b0),
    .USER_CHANNEL_DRPEN_IN (1'b0),
    .USER_CHANNEL_DRPWE_IN (1'b0),
    .USER_CHANNEL_DRPRDY_OUT (),
    .USER_CHANNEL_DRPDO_OUT (),
    .CPLL_CAL_FAIL (),
    .CPLL_CAL_DONE (),
    .DEBUG_OUT (),
    .CAL_FREQ_CNT (),
    .REPEAT_RESET_LIMIT (4'd15),
    .GTYE4_TXOUTCLK_IN (1'b0),
    .GTYE4_CPLLLOCK_IN (1'b0),
    .GTYE4_CPLLRESET_OUT (),
    .GTYE4_CPLLPD_OUT (),
    .GTYE4_TXPROGDIVRESET_OUT (),
    .GTYE4_TXOUTCLKSEL_OUT (),
    .GTYE4_TXPRGDIVRESETDONE_IN (1'b0),
    .GTYE4_CHANNEL_DRPADDR_OUT (),
    .GTYE4_CHANNEL_DRPDI_OUT (),
    .GTYE4_CHANNEL_DRPEN_OUT (),
    .GTYE4_CHANNEL_DRPWE_OUT (),
    .GTYE4_CHANNEL_DRPRDY_IN (1'b0),
    .GTYE4_CHANNEL_DRPDO_IN (16'b0)
    );
    end
    //GD if (0) begin : gen_cpll_cal_gtye4
    //GD
    //GD gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal #(
    //GD .C_SIM_CPLL_CAL_BYPASS(
    //GD //pragma translate_off
    //GD C_SIM_CPLL_CAL_BYPASS ||
    //GD //pragma translate_on
    //GD 1'b0
    //GD ),
    //GD .C_PCIE_ENABLE(C_PCIE_ENABLE),
    //GD .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
    //GD .C_RX_PLL_TYPE(C_RX_PLL_TYPE),
    //GD .C_TX_PLL_TYPE(C_TX_PLL_TYPE),
    //GD .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ)
    //GD ) gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst (
    //GD .TXOUTCLK_PERIOD_IN (18'b0),
    //GD .WAIT_DEASSERT_CPLLPD_IN (16'b0),
    //GD .CNT_TOL_IN (18'b0),
    //GD .FREQ_COUNT_WINDOW_IN (16'b0),
    //GD .RESET_IN (1'b0),
    //GD .CLK_IN (1'b0),
    //GD .DRPRST_IN (1'b0),
    //GD .USER_TXOUTCLK_BUFG_CE_IN (1'b0),
    //GD .USER_TXOUTCLK_BUFG_CLR_IN (1'b0),
    //GD .USER_TXPROGDIVRESET_IN (1'b0),
    //GD .GTYE4_RXOUTCLK_IN (1'b0),
    //GD .GTYE4_RXPMARESETDONE_IN (1'b0),
    //GD .GTYE4_RXPRGDIVRESETDONE_IN (1'b0),
    //GD .USER_GTRXRESET_IN (1'b0),
    //GD .USER_RXCDRHOLD_IN (1'b0),
    //GD .USER_RXOUTCLK_BUFG_CE_IN (1'b0),
    //GD .USER_RXOUTCLK_BUFG_CLR_IN (1'b0),
    //GD .USER_RXPMARESET_IN (1'b0),
    //GD .USER_RXPROGDIVRESET_IN (1'b0),
    //GD .USER_RXPLLCLKSEL (2'b00),
    //GD .USER_TXPLLCLKSEL (2'b00),
    //GD .USER_RXOUTCLKSEL_IN (3'b010),
    //GD .GTYE4_GTRXRESET_OUT (),
    //GD .GTYE4_RXCDRHOLD_OUT (),
    //GD .GTYE4_RXPMARESET_OUT (),
    //GD .GTYE4_RXPROGDIVRESET_OUT (),
    //GD .USER_RXPMARESETDONE_OUT (),
    //GD .USER_RXPRGDIVRESETDONE_OUT (),
    //GD .GTYE4_RXOUTCLKSEL_OUT (),
    //GD .USER_TXPRGDIVRESETDONE_OUT (),
    //GD .USER_TXOUTCLKSEL_IN (3'b0),
    //GD .USER_CPLLLOCK_OUT (),
    //GD .USER_CHANNEL_DRPADDR_IN (9'b0),
    //GD .USER_CHANNEL_DRPDI_IN (16'b0),
    //GD .USER_CHANNEL_DRPEN_IN (1'b0),
    //GD .USER_CHANNEL_DRPWE_IN (1'b0),
    //GD .USER_CHANNEL_DRPRDY_OUT (),
    //GD .USER_CHANNEL_DRPDO_OUT (),
    //GD .CPLL_CAL_FAIL (),
    //GD .CPLL_CAL_DONE (),
    //GD .DEBUG_OUT (),
    //GD .CAL_FREQ_CNT (),
    //GD .REPEAT_RESET_LIMIT (4'd15),
    //GD .GTYE4_TXOUTCLK_IN (1'b0),
    //GD .GTYE4_CPLLLOCK_IN (1'b0),
    //GD .GTYE4_CPLLRESET_OUT (),
    //GD .GTYE4_CPLLPD_OUT (),
    //GD .GTYE4_TXPROGDIVRESET_OUT (),
    //GD .GTYE4_TXOUTCLKSEL_OUT (),
    //GD .GTYE4_TXPRGDIVRESETDONE_IN (1'b0),
    //GD .GTYE4_CHANNEL_DRPADDR_OUT (),
    //GD .GTYE4_CHANNEL_DRPDI_OUT (),
    //GD .GTYE4_CHANNEL_DRPEN_OUT (),
    //GD .GTYE4_CHANNEL_DRPWE_OUT (),
    //GD .GTYE4_CHANNEL_DRPRDY_IN (1'b0),
    //GD .GTYE4_CHANNEL_DRPDO_IN (16'b0)
    //GD );
    //GD
    //GD end
    genvar pwrgood_delay;
    for (pwrgood_delay = 0; pwrgood_delay < `gtwizard_ultrascale_2_gtwizard_gthe4_N_CH; pwrgood_delay = pwrgood_delay + 1) begin : gen_pwrgood_delay_inst
    ......
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v
    View file @ 983726db
    This source diff could not be displayed because it is too large. You can view the blob instead.
    platform/xilinx/xwrc_platform_vivado.vhd
    View file @ 983726db
    ......@@ -189,7 +189,8 @@ begin -- architecture rtl
    -----------------------------------------------------------------------------
    -- Check for unsupported features and/or misconfiguration
    -----------------------------------------------------------------------------
    gen_unknown_fpga : if (g_fpga_family /= "kintex7" and g_fpga_family /= "artix7" and g_fpga_family /= "zynqus") generate
    gen_unknown_fpga : if (g_fpga_family /= "kintex7" and g_fpga_family /=
    "artix7" and g_fpga_family /= "zynqus" and g_fpga_family /= "zynqus_epll") generate
    assert FALSE
    report "Xilinx FPGA family [" & g_fpga_family & "] is not supported"
    severity ERROR;
    ......@@ -547,6 +548,25 @@ begin -- architecture rtl
    end generate gen_zynqus_default_plls;
    ---------------------------------------------------------------------------
    -- Zynq US+ Buffers when external PLLs are used
    ---------------------------------------------------------------------------
    gen_zynqus_si5341_plls: if (g_fpga_family = "zynqus_epll") generate
    cmp_clk_ref_buf: BUFG
    port map (
    I => clk_125m_pllref_i, -- 62.5MHz in DI/OT
    O => clk_sys);
    clk_62m5_sys_o <= clk_sys;
    pll_locked_o <= '1'; --pll_sys_locked;
    cmp_clk_dmtd_buf_o: BUFG
    port map (
    O => clk_62m5_dmtd_o,
    I => clk_125m_dmtd_i);
    end generate gen_zynqus_si5341_plls;
    ---------------------------------------------------------------------------
    gen_no_ext_ref_pll : if (g_with_external_clock_input = FALSE) generate
    ......@@ -739,7 +759,7 @@ begin -- architecture rtl
    ---------------------------------------------------------------------------
    -- ZynqUS+ PHY
    ---------------------------------------------------------------------------
    gen_phy_zynqus : if (g_fpga_family = "zynqus") generate
    gen_phy_zynqus : if (g_fpga_family = "zynqus" or g_fpga_family = "zynqus_epll") generate
    signal clk_125m_gth_buf : std_logic;
    signal clk_ref : std_logic;
    ......
    syn/diot_wr_mpsoc/README 0 → 100644
    View file @ 983726db
    To create Xilinx project for DI/OT System Board execute:
    $ vivado -mode batch -source build.tcl
    syn/diot_wr_mpsoc/build.tcl 0 → 100644
    View file @ 983726db
    # Create Vivado project
    source ../../top/diot_wr_mpsoc/diot_wr_mpsoc.tcl
    # Generate the wrapper
    set design_name design_1
    make_wrapper -files [get_files $design_name.bd] -top -import
    # Make this newly generated wrapper our new TOP
    set file "hdl/design_1_wrapper.vhd"
    set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
    set_property -name "file_type" -value "VHDL" -objects $file_obj
    # Set 'sources_1' fileset properties
    set obj [get_filesets sources_1]
    set_property -name "top" -value "design_1_wrapper" -objects $obj
    set_property -name "top_auto_set" -value "0" -objects $obj
    top/diot_wr_mpsoc/diot_bd.tcl 0 → 100644
    View file @ 983726db
    This diff is collapsed.
    top/diot_wr_mpsoc/diot_ps_config.tcl 0 → 100644
    View file @ 983726db
    This diff is collapsed.
    top/diot_wr_mpsoc/diot_wr_mpsoc.tcl 0 → 100644
    View file @ 983726db
    This diff is collapsed.
    top/diot_wr_mpsoc/diot_wr_mpsoc.xdc 0 → 100644
    View file @ 983726db
    set_property PACKAGE_PIN K22 [get_ports {BOARD_SCL_0[0]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {BOARD_SCL_0[0]}]
    set_property PACKAGE_PIN J20 [get_ports {BOARD_SDA_0[0]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {BOARD_SDA_0[0]}]
    set_property PACKAGE_PIN AL12 [get_ports {EEPROM_SCL[0]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {EEPROM_SCL[0]}]
    set_property PACKAGE_PIN AT15 [get_ports {EEPROM_SDA_0[0]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {EEPROM_SDA_0[0]}]
    set_property PACKAGE_PIN K27 [get_ports led_act_o_0]
    set_property IOSTANDARD LVCMOS18 [get_ports led_act_o_0]
    set_property PACKAGE_PIN J30 [get_ports led_link_o_0]
    set_property IOSTANDARD LVCMOS18 [get_ports led_link_o_0]
    set_property PACKAGE_PIN L13 [get_ports pll20dac_cs_n_o_0]
    set_property PACKAGE_PIN L12 [get_ports pll25dac_cs_n_o_0]
    set_property IOSTANDARD LVCMOS33 [get_ports pll20dac_cs_n_o_0]
    set_property IOSTANDARD LVCMOS33 [get_ports pll25dac_cs_n_o_0]
    set_property PACKAGE_PIN K14 [get_ports plldac_din_o_0]
    set_property PACKAGE_PIN K13 [get_ports plldac_sclk_o_0]
    set_property PACKAGE_PIN AL26 [get_ports pps_led_o_0]
    set_property PACKAGE_PIN F13 [get_ports pps_p_o_0]
    set_property IOSTANDARD LVCMOS33 [get_ports pps_p_o_0]
    set_property PACKAGE_PIN K18 [get_ports sfp_los_i_0]
    set_property PACKAGE_PIN AJ4 [get_ports sfp_rxp_i_0]
    set_property PACKAGE_PIN D19 [get_ports uart_rxd_i_0]
    set_property PACKAGE_PIN D20 [get_ports uart_txd_o_0]
    set_property IOSTANDARD LVCMOS18 [get_ports uart_rxd_i_0]
    set_property IOSTANDARD LVCMOS18 [get_ports uart_txd_o_0]
    set_property PACKAGE_PIN E14 [get_ports wr_clk_helper_62_5m_p_i_0]
    set_property PACKAGE_PIN E15 [get_ports wr_clk_main_62_5m_p_i_0]
    set_property IOSTANDARD LVDS_25 [get_ports wr_clk_helper_62_5m_p_i_0]
    set_property IOSTANDARD LVDS_25 [get_ports wr_clk_helper_62_5m_n_i_0]
    set_property IOSTANDARD LVDS_25 [get_ports wr_clk_main_62_5m_p_i_0]
    set_property IOSTANDARD LVDS_25 [get_ports wr_clk_main_62_5m_n_i_0]
    set_property PACKAGE_PIN AH10 [get_ports wr_clk_sfp_125m_p_i_0]
    set_property IOSTANDARD LVCMOS18 [get_ports sfp_los_i_0]
    set_property IOSTANDARD LVCMOS18 [get_ports pps_led_o_0]
    set_property IOSTANDARD LVCMOS33 [get_ports plldac_sclk_o_0]
    set_property IOSTANDARD LVCMOS33 [get_ports plldac_din_o_0]
    set_property PACKAGE_PIN AH23 [get_ports sfp_det_i_0]
    set_property IOSTANDARD LVCMOS18 [get_ports sfp_det_i_0]
    create_clock -period 16.000 -name clk_helper -waveform {0.000 8.000} [get_ports wr_clk_helper_62_5m_p_i_0]
    create_clock -period 16.000 -name clk_main -waveform {0.000 8.000} [get_ports wr_clk_main_62_5m_p_i_0]
    create_clock -period 8.000 -name clk_sfp -waveform {0.000 4.000} [get_ports wr_clk_sfp_125m_p_i_0]
    create_clock -period 16.000 -name clk_rx -waveform {0.000 8.000} [get_nets {design_1_i/wrc_board_diot_simple_0/U0/cmp_xwrc_platform/gen_phy_zynqus.cmp_gth/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0]}]
    create_clock -period 16.000 -name clk_tx -waveform {0.000 8.000} [get_nets design_1_i/wrc_board_diot_simple_0/U0/cmp_xwrc_platform/gen_phy_zynqus.cmp_gth/tx_out_clk_o]
    set_clock_groups -asynchronous -group [get_clocks *helper*] -group [get_clocks *clk_main*] -group [get_clocks *clk_sfp*] -group [get_clocks *clk_rx*] -group [get_clocks clk_tx]
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