Commit c63228b6 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wr_core: hold LM32 reset active when the CPU doesn't have a preloaded firmware

parent bba3432e
Pipeline #812 passed with stage
in 25 seconds
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2020-11-02
-- Last update: 2021-01-15
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -345,7 +345,7 @@ architecture struct of wr_core is
function f_check_if_lm32_firmware_necessary return boolean is
begin
if(g_dpram_initf /= "") then
if(g_dpram_initf /= "" and g_dpram_initf /= "none") then
return true;
else
return false;
......@@ -452,6 +452,8 @@ architecture struct of wr_core is
signal secbar_master_i : t_wishbone_master_in_array(8 downto 0);
signal secbar_master_o : t_wishbone_master_out_array(8 downto 0);
impure function f_pick_secbar_base return std_logic_vector is
begin
if g_ram_address_space_size_kb = 128 then
......@@ -483,6 +485,15 @@ architecture struct of wr_core is
signal cbar_master_i : t_wishbone_master_in_array(1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(1 downto 0);
attribute mark_debug : string;
attribute mark_debug of cbar_master_o : signal is "true";
attribute mark_debug of cbar_master_i : signal is "true";
attribute mark_debug of cbar_slave_o : signal is "true";
attribute mark_debug of cbar_slave_i : signal is "true";
attribute mark_debug of secbar_master_o : signal is "true";
attribute mark_debug of secbar_master_i : signal is "true";
-----------------------------------------------------------------------------
--External WB interface
-----------------------------------------------------------------------------
......@@ -930,6 +941,7 @@ begin
g_board_name => g_board_name,
g_flash_secsz_kb => g_flash_secsz_kb,
g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
g_has_preinitialized_firmware => f_check_if_lm32_firmware_necessary,
g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart,
g_mem_words => g_dpram_size,
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-04-04
-- Last update: 2020-08-19
-- Last update: 2021-01-15
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -51,6 +51,7 @@ entity wrc_periph is
g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
g_phys_uart : boolean := true;
g_has_preinitialized_firmware : boolean;
g_with_phys_uart_fifo : boolean := false;
g_phys_uart_tx_fifo_size : integer := 1024;
g_phys_uart_rx_fifo_size : integer := 1024;
......@@ -151,7 +152,14 @@ begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
rst_net_n_o <= '0';
rst_wrc_n_o_reg <= '1';
if g_has_preinitialized_firmware then
rst_wrc_n_o_reg <= '1';
else
rst_wrc_n_o_reg <= '0'; -- no firmware in DPRAM? keep in reset so
-- that the CPU doesn't walk through the
-- whole address space trying to fetch
-- instructions (and sometimes freezing the interconnect)
end if;
else
if(sysc_regs_o.rstr_trig_wr_o = '1' and sysc_regs_o.rstr_trig_o = x"deadbee") then
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11
-- Last update: 2020-11-02
-- Last update: 2021-01-15
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -245,6 +245,7 @@ package wrcore_pkg is
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 64;
g_flash_sdbfs_baddr : integer := 16#2e0000#;
g_has_preinitialized_firmware : boolean;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_cntr_period : integer := 62500;
......
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