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White Rabbit core collection
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1435aa3e
Commit
1435aa3e
authored
Jan 26, 2021
by
Tomasz Wlostowski
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wr_si57x_interface: add BUSY flag and full N1/HSDIV configuration to register block
parent
fb25a444
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3 changed files
with
23 additions
and
34 deletions
+23
-34
si570_if_wb.vhd
modules/wr_si57x_interface/si570_if_wb.vhd
+7
-30
si570_if_wb.wb
modules/wr_si57x_interface/si570_if_wb.wb
+11
-2
si570_if_wbgen2_pkg.vhd
modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
+5
-2
No files found.
modules/wr_si57x_interface/si570_if_wb.vhd
View file @
1435aa3e
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : si570_if_wb.vhd
-- Author : auto-generated by wbgen2 from si570_if_wb.wb
-- Created : T
hu Mar 12 23:41:40 2020
-- Created : T
ue Jan 26 15:18:39 2021
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE si570_if_wb.wb
...
...
@@ -44,7 +44,7 @@ signal si570_cr_enable_int : std_logic ;
signal
si570_cr_gain_int
:
std_logic_vector
(
7
downto
0
);
signal
si570_cr_clk_div_int
:
std_logic_vector
(
7
downto
0
);
signal
si570_rfreql_int
:
std_logic_vector
(
31
downto
0
);
signal
si570_rfreqh_int
:
std_logic_vector
(
7
downto
0
);
signal
si570_rfreqh_int
:
std_logic_vector
(
31
downto
0
);
signal
si570_gpcr_scl_dly0
:
std_logic
;
signal
si570_gpcr_scl_int
:
std_logic
;
signal
si570_gpcr_sda_dly0
:
std_logic
;
...
...
@@ -76,7 +76,7 @@ begin
si570_cr_gain_int
<=
"00000000"
;
si570_cr_clk_div_int
<=
"00000000"
;
si570_rfreql_int
<=
"00000000000000000000000000000000"
;
si570_rfreqh_int
<=
"00000000"
;
si570_rfreqh_int
<=
"00000000
000000000000000000000000
"
;
regs_o
.
gpsr_scl_load_o
<=
'0'
;
regs_o
.
gpsr_sda_load_o
<=
'0'
;
si570_gpcr_scl_int
<=
'0'
;
...
...
@@ -110,7 +110,7 @@ begin
rddata_reg
(
8
)
<=
si570_cr_enable_int
;
rddata_reg
(
16
downto
9
)
<=
si570_cr_gain_int
;
rddata_reg
(
24
downto
17
)
<=
si570_cr_clk_div_int
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
25
)
<=
regs_i
.
cr_busy_i
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
...
...
@@ -128,33 +128,9 @@ begin
ack_in_progress
<=
'1'
;
when
"010"
=>
if
(
wb_we_i
=
'1'
)
then
si570_rfreqh_int
<=
wrdata_reg
(
7
downto
0
);
si570_rfreqh_int
<=
wrdata_reg
(
31
downto
0
);
end
if
;
rddata_reg
(
7
downto
0
)
<=
si570_rfreqh_int
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
31
downto
0
)
<=
si570_rfreqh_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011"
=>
...
...
@@ -258,6 +234,7 @@ regs_o.cr_enable_o <= si570_cr_enable_int;
regs_o
.
cr_gain_o
<=
si570_cr_gain_int
;
-- I2C Clock Divider
regs_o
.
cr_clk_div_o
<=
si570_cr_clk_div_int
;
-- Si57x I/F Busy
-- RFREQ low part
regs_o
.
rfreql_o
<=
si570_rfreql_int
;
-- RFREQ hi part
...
...
modules/wr_si57x_interface/si570_if_wb.wb
View file @
1435aa3e
...
...
@@ -43,7 +43,16 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
field {
name = "Si57x I/F Busy";
prefix = "BUSY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
...
...
@@ -65,7 +74,7 @@ peripheral {
field {
name = "RFREQ hi part";
size =
8
;
size =
32
;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
...
...
modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
View file @
1435aa3e
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : si570_if_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from si570_if_wb.wb
-- Created : T
hu Mar 12 23:41:40 2020
-- Created : T
ue Jan 26 15:18:39 2021
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE si570_if_wb.wb
...
...
@@ -20,11 +20,13 @@ package si570_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type
t_si570_in_registers
is
record
cr_busy_i
:
std_logic
;
gpsr_scl_i
:
std_logic
;
gpsr_sda_i
:
std_logic
;
end
record
;
constant
c_si570_in_registers_init_value
:
t_si570_in_registers
:
=
(
cr_busy_i
=>
'0'
,
gpsr_scl_i
=>
'0'
,
gpsr_sda_i
=>
'0'
);
...
...
@@ -37,7 +39,7 @@ package si570_wbgen2_pkg is
cr_gain_o
:
std_logic_vector
(
7
downto
0
);
cr_clk_div_o
:
std_logic_vector
(
7
downto
0
);
rfreql_o
:
std_logic_vector
(
31
downto
0
);
rfreqh_o
:
std_logic_vector
(
7
downto
0
);
rfreqh_o
:
std_logic_vector
(
31
downto
0
);
gpsr_scl_o
:
std_logic
;
gpsr_scl_load_o
:
std_logic
;
gpsr_sda_o
:
std_logic
;
...
...
@@ -113,6 +115,7 @@ end function;
function
"or"
(
left
,
right
:
t_si570_in_registers
)
return
t_si570_in_registers
is
variable
tmp
:
t_si570_in_registers
;
begin
tmp
.
cr_busy_i
:
=
f_x_to_zero
(
left
.
cr_busy_i
)
or
f_x_to_zero
(
right
.
cr_busy_i
);
tmp
.
gpsr_scl_i
:
=
f_x_to_zero
(
left
.
gpsr_scl_i
)
or
f_x_to_zero
(
right
.
gpsr_scl_i
);
tmp
.
gpsr_sda_i
:
=
f_x_to_zero
(
left
.
gpsr_sda_i
)
or
f_x_to_zero
(
right
.
gpsr_sda_i
);
return
tmp
;
...
...
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