Commit d569b726 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

platform/xilinx: don't constrain clock frequencies in the GTHE4 XDC file, they…

platform/xilinx: don't constrain clock frequencies in the GTHE4 XDC file, they are already set in the top level XDC
parent 5e0ea46e
Pipeline #3085 failed with stage
in 0 seconds
......@@ -205,7 +205,7 @@ begin
U_Sync2 : gc_sync_ffs
port map (
clk_i => tx_clk,
clk_i => rx_clk,
rst_n_i => rst_n,
data_i => gtwiz_buffbypass_rx_reset_pre,
synced_o => gtwiz_buffbypass_rx_reset_in);
......
......@@ -54,13 +54,13 @@
# OOC Synthesis and Hierarchical Designs.
# Free-running clock constraint
create_clock -period 16.0 [get_ports gtwiz_reset_clk_freerun_in]
#create_clock -period 16.0 [get_ports gtwiz_reset_clk_freerun_in]
# CPLL reference clock constraint (will be overridden by required constraint on IBUFDS_GTE4 input in context)
create_clock -period 8.0 [get_ports gtrefclk0_in[0]]
#create_clock -period 8.0 [get_ports gtrefclk0_in[0]]
# DRP clock constraint for CHANNEL primitive
create_clock -period 16.0 [get_ports drpclk_in[0]]
#create_clock -period 16.0 [get_ports drpclk_in[0]]
##set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}] -quiet
......
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