adding top project for DI/OT System Board

6e64fab1 · Grzegorz Daniluk · 46af05ad · 6e64fab1 · 6e64fab1 · 6e64fab1
Commit 6e64fab1 authored May 07, 2021 by Grzegorz Daniluk
6 changed files
--- a/syn/diot_wr_mpsoc/README
+++ b/syn/diot_wr_mpsoc/README
+To create Xilinx project for DI/OT System Board execute:
+$ vivado -mode batch -source build.tcl
--- a/syn/diot_wr_mpsoc/build.tcl
+++ b/syn/diot_wr_mpsoc/build.tcl
+# Create Vivado project
+source ../../top/diot_wr_mpsoc/diot_wr_mpsoc.tcl
+
+# Generate the wrapper
+set design_name design_1
+make_wrapper -files [get_files $design_name.bd] -top -import
+
+# Make this newly generated wrapper our new TOP
+set file "hdl/design_1_wrapper.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "design_1_wrapper" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
--- a/top/diot_wr_mpsoc/diot_bd.tcl
+++ b/top/diot_wr_mpsoc/diot_bd.tcl
--- a/top/diot_wr_mpsoc/diot_ps_config.tcl
+++ b/top/diot_wr_mpsoc/diot_ps_config.tcl
--- a/top/diot_wr_mpsoc/diot_wr_mpsoc.tcl
+++ b/top/diot_wr_mpsoc/diot_wr_mpsoc.tcl
--- a/top/diot_wr_mpsoc/diot_wr_mpsoc.xdc
+++ b/top/diot_wr_mpsoc/diot_wr_mpsoc.xdc
+set_property PACKAGE_PIN K22 [get_ports {BOARD_SCL_0[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {BOARD_SCL_0[0]}]
+set_property PACKAGE_PIN J20 [get_ports {BOARD_SDA_0[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {BOARD_SDA_0[0]}]
+set_property PACKAGE_PIN AL12 [get_ports {EEPROM_SCL[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EEPROM_SCL[0]}]
+set_property PACKAGE_PIN AT15 [get_ports {EEPROM_SDA_0[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EEPROM_SDA_0[0]}]
+
+set_property PACKAGE_PIN K27 [get_ports led_act_o_0]
+set_property IOSTANDARD LVCMOS18 [get_ports led_act_o_0]
+set_property PACKAGE_PIN J30 [get_ports led_link_o_0]
+set_property IOSTANDARD LVCMOS18 [get_ports led_link_o_0]
+set_property PACKAGE_PIN L13 [get_ports pll20dac_cs_n_o_0]
+set_property PACKAGE_PIN L12 [get_ports pll25dac_cs_n_o_0]
+set_property IOSTANDARD LVCMOS33 [get_ports pll20dac_cs_n_o_0]
+set_property IOSTANDARD LVCMOS33 [get_ports pll25dac_cs_n_o_0]
+set_property PACKAGE_PIN K14 [get_ports plldac_din_o_0]
+set_property PACKAGE_PIN K13 [get_ports plldac_sclk_o_0]
+set_property PACKAGE_PIN AL26 [get_ports pps_led_o_0]
+set_property PACKAGE_PIN F13 [get_ports pps_p_o_0]
+set_property IOSTANDARD LVCMOS33 [get_ports pps_p_o_0]
+set_property PACKAGE_PIN K18 [get_ports sfp_los_i_0]
+set_property PACKAGE_PIN AJ4 [get_ports sfp_rxp_i_0]
+set_property PACKAGE_PIN D19 [get_ports uart_rxd_i_0]
+set_property PACKAGE_PIN D20 [get_ports uart_txd_o_0]
+set_property IOSTANDARD LVCMOS18 [get_ports uart_rxd_i_0]
+set_property IOSTANDARD LVCMOS18 [get_ports uart_txd_o_0]
+set_property PACKAGE_PIN E14 [get_ports wr_clk_helper_62_5m_p_i_0]
+set_property PACKAGE_PIN E15 [get_ports wr_clk_main_62_5m_p_i_0]
+set_property IOSTANDARD LVDS_25 [get_ports wr_clk_helper_62_5m_p_i_0]
+set_property IOSTANDARD LVDS_25 [get_ports wr_clk_helper_62_5m_n_i_0]
+set_property IOSTANDARD LVDS_25 [get_ports wr_clk_main_62_5m_p_i_0]
+set_property IOSTANDARD LVDS_25 [get_ports wr_clk_main_62_5m_n_i_0]
+set_property PACKAGE_PIN AH10 [get_ports wr_clk_sfp_125m_p_i_0]
+set_property IOSTANDARD LVCMOS18 [get_ports sfp_los_i_0]
+set_property IOSTANDARD LVCMOS18 [get_ports pps_led_o_0]
+set_property IOSTANDARD LVCMOS33 [get_ports plldac_sclk_o_0]
+set_property IOSTANDARD LVCMOS33 [get_ports plldac_din_o_0]
+set_property PACKAGE_PIN AH23 [get_ports sfp_det_i_0]
+set_property IOSTANDARD LVCMOS18 [get_ports sfp_det_i_0]
+
+create_clock -period 16.000 -name clk_helper -waveform {0.000 8.000} [get_ports wr_clk_helper_62_5m_p_i_0]
+create_clock -period 16.000 -name clk_main -waveform {0.000 8.000} [get_ports wr_clk_main_62_5m_p_i_0]
+create_clock -period 8.000 -name clk_sfp -waveform {0.000 4.000} [get_ports wr_clk_sfp_125m_p_i_0]
+create_clock -period 16.000 -name clk_rx -waveform {0.000 8.000} [get_nets {design_1_i/wrc_board_diot_simple_0/U0/cmp_xwrc_platform/gen_phy_zynqus.cmp_gth/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0]}]
+create_clock -period 16.000 -name clk_tx -waveform {0.000 8.000} [get_nets design_1_i/wrc_board_diot_simple_0/U0/cmp_xwrc_platform/gen_phy_zynqus.cmp_gth/tx_out_clk_o]
+set_clock_groups -asynchronous -group [get_clocks *helper*] -group [get_clocks *clk_main*] -group [get_clocks *clk_sfp*] -group [get_clocks *clk_rx*] -group [get_clocks clk_tx]
+
+
+
+