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White Rabbit core collection
Commit 60efefe9 authored by Maciej Lipinski's avatar Maciej Lipinski
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[Virtex5 PHY] clean up resets 

- generate common (ch0 & ch1) reset synched with ch01_ref_clk_i
- ch0_gtp_reset and ch1_gtp_reset were not driven
- and some more cleaing
parent bc3621a8
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Showing with 23 additions and 17 deletions
platform/xilinx/wr_gtp_phy/virtex5/wr_gtp_phy_virtex5.vhd
View file @ 60efefe9
......@@ -68,12 +68,13 @@ entity wr_gtp_phy_virtex5 is
-- dedicated GTP clock input
gtp_clk_i : in std_logic;
rst_i : in std_logic;
-- CLOCK MUST BE PRESENT AT RESET TIME!
-- TX path, synchronous to ch01_ref_clk_i
ch01_ref_clk_i : in std_logic := '0';
-- reset input, active hi
ch01_ref_clk_rst_i : in std_logic := '0';
-- Port 0
-- TX path, synchronous to ch0_ref_clk_i
-- ch0_ref_clk_i : in std_logic := '0';
......@@ -316,7 +317,6 @@ architecture rtl of wr_gtp_phy_virtex5 is
signal ch0_rx_enable_output, ch0_rx_enable_output_synced : std_logic;
signal ch1_gtp_reset : std_logic;
signal ch1_gtp_loopback : std_logic_vector(2 downto 0) := "000";
signal ch1_gtp_reset_done : std_logic;
......@@ -400,14 +400,14 @@ begin -- rtl
rstn_o(0) => ch1_gtp_reset_rxclk_n);
ch1_gtp_reset_rxclk <= not ch1_gtp_reset_rxclk_n;
ch01_gtp_reset <= ch01_rst_synced or std_logic(not ch01_reset_counter(ch01_reset_counter'left));
p_gen_reset : process(ch01_ref_clk_i)
begin
if rising_edge(ch01_ref_clk_i) then
ch01_rst_d0 <= rst_i;
ch01_rst_d0 <= ch01_ref_clk_rst_i;
ch01_rst_synced <= ch01_rst_d0;
if(ch01_rst_synced = '1') then
......@@ -526,9 +526,9 @@ begin -- rtl
npulse_o => open,
ppulse_o => open);
p_force_proper_disparity_ch0 : process(ch01_ref_clk_i, ch0_gtp_reset)
p_force_proper_disparity_ch0 : process(ch01_ref_clk_i, ch01_gtp_reset)
begin
if (ch0_gtp_reset = '1') then
if (ch01_gtp_reset = '1') then
ch0_disparity_set <= '0';
ch0_tx_chardispval <= '0';
ch0_tx_chardispmode <= '0';
......@@ -548,9 +548,9 @@ begin -- rtl
end if;
end process;
p_gen_output_ch0 : process(ch0_rx_rec_clk, ch0_gtp_reset)
p_gen_output_ch0 : process(ch0_rx_rec_clk, ch0_gtp_reset_rxclk)
begin
if(ch0_gtp_reset = '1') then
if(ch0_gtp_reset_rxclk = '1') then
ch0_rx_data_o <= (others => '0');
ch0_rx_k_o <= '0';
ch0_rx_enc_err_o <= '0';
......@@ -694,9 +694,9 @@ begin -- rtl
npulse_o => open,
ppulse_o => open);
p_force_proper_disparity_ch1 : process(ch01_ref_clk_i, ch1_gtp_reset)
p_force_proper_disparity_ch1 : process(ch01_ref_clk_i, ch01_gtp_reset)
begin
if (ch1_gtp_reset = '1') then
if (ch01_gtp_reset = '1') then
ch1_disparity_set <= '0';
ch1_tx_chardispval <= '0';
ch1_tx_chardispmode <= '0';
......@@ -717,9 +717,9 @@ begin -- rtl
end if;
end process;
p_gen_output_ch1 : process(ch1_rx_rec_clk, rst_i)
p_gen_output_ch1 : process(ch1_rx_rec_clk, ch1_gtp_reset_rxclk)
begin
if(rst_i = '1') then
if(ch1_gtp_reset_rxclk = '1') then
ch1_rx_data_o <= (others => '0');
ch1_rx_k_o <= '0';
ch1_rx_enc_err_o <= '0';
......@@ -851,6 +851,7 @@ begin -- rtl
-- ML:
ch0_rdy_o <= '1'; -- todo
ch1_rdy_o <= '1'; -- todo
-- ch0_rdy <= ch01_gtp_locked and ch01_align_done when (g_enable_ch0 = 1) else '0';
-- ch1_rdy <= ch01_gtp_locked and ch01_align_done when (g_enable_ch1 = 1) else '0';
--
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ 60efefe9
......@@ -173,6 +173,7 @@ package wr_xilinx_pkg is
port (
gtp_clk_i : in std_logic;
ch01_ref_clk_i : in std_logic := '0';
ch01_ref_clk_rst_i : in std_logic := '0';
ch0_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch0_tx_k_i : in std_logic := '0';
ch0_tx_disparity_o : out std_logic;
......@@ -182,7 +183,6 @@ package wr_xilinx_pkg is
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch0_rdy_o : out std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
......@@ -194,7 +194,6 @@ package wr_xilinx_pkg is
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
ch1_rdy_o : out std_logic;
pad_txn0_o : out std_logic;
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ 60efefe9
......@@ -963,6 +963,7 @@ begin -- architecture rtl
signal ch1_sfp_txn, ch1_sfp_txp : std_logic;
signal ch0_sfp_rxn, ch0_sfp_rxp : std_logic;
signal ch1_sfp_rxn, ch1_sfp_rxp : std_logic;
signal ch01_ref_clk_rst : std_logic;
begin
......@@ -976,6 +977,12 @@ begin -- architecture rtl
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i);
cmp_gtp_rst : gc_sync_ffs
port map (
clk_i => clk_125m_pllref_buf,
rst_n_i => '1',
data_i => phy8_i.rst,
synced_o => ch01_ref_clk_rst);
cmp_gtp : wr_gtp_phy_virtex5
generic map (
......@@ -985,6 +992,7 @@ begin -- architecture rtl
port map (
gtp_clk_i => clk_125m_gtp_buf,
ch01_ref_clk_i => clk_125m_pllref_buf,
ch01_ref_clk_rst_i => ch01_ref_clk_rst,
ch0_tx_data_i => phy8_i.tx_data,
ch0_tx_k_i => phy8_i.tx_k(0),
ch0_tx_disparity_o => ch0_phy8_out.tx_disparity,
......@@ -994,7 +1002,6 @@ begin -- architecture rtl
ch0_rx_k_o => ch0_phy8_out.rx_k(0),
ch0_rx_enc_err_o => ch0_phy8_out.rx_enc_err,
ch0_rx_bitslide_o => ch0_phy8_out.rx_bitslide,
ch0_rst_i => phy8_i.rst,
ch0_loopen_i => phy8_i.loopen,
ch0_rdy_o => ch0_phy8_out.rdy,
ch1_tx_data_i => phy8_i.tx_data,
......@@ -1006,7 +1013,6 @@ begin -- architecture rtl
ch1_rx_k_o => ch1_phy8_out.rx_k(0),
ch1_rx_enc_err_o => ch1_phy8_out.rx_enc_err,
ch1_rx_bitslide_o => ch1_phy8_out.rx_bitslide,
ch1_rst_i => phy8_i.rst,
ch1_loopen_i => phy8_i.loopen,
ch1_rdy_o => ch1_phy8_out.rdy,
pad_txn0_o => ch0_sfp_txn,
......
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