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White Rabbit core collection
Commit 34a55986 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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modules/wr_streamers: make DBG_WORD optional (generic parameter). Remove… 

modules/wr_streamers: make DBG_WORD optional (generic parameter). Remove MARK_DEBUG attributes to facilitate timing closure
parent 092a8885
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Showing with 36 additions and 30 deletions
modules/wr_streamers/streamers_pkg.vhd
View file @ 34a55986
......@@ -335,7 +335,8 @@ package streamers_pkg is
g_slave_mode : t_wishbone_interface_mode := CLASSIC;
g_slave_granularity : t_wishbone_address_granularity := BYTE;
g_simulation : integer := 0;
g_sim_cycle_counter_range : integer := 125000
g_sim_cycle_counter_range : integer := 125000;
g_with_dbg_word : boolean := TRUE
);
port (
......
modules/wr_streamers/xrx_streamer.vhd
View file @ 34a55986
......@@ -186,14 +186,14 @@ architecture rtl of xrx_streamer is
signal fifo_sync, fifo_last, frames_lost, blocks_lost : std_logic;
signal fifo_dout, fifo_din : std_logic_vector(g_data_width + 1 + 28 + 1 downto 0);
attribute mark_debug : string;
attribute mark_debug of fifo_drop : signal is "true";
attribute mark_debug of fifo_accept : signal is "true";
attribute mark_debug of fifo_dvalid : signal is "true";
attribute mark_debug of state : signal is "true";
attribute mark_debug of fsm_in : signal is "true";
attribute mark_debug of fifo_full : signal is "true";
attribute mark_debug of fifo_dreq : signal is "true";
--attribute mark_debug : string;
--attribute mark_debug of fifo_drop : signal is "true";
--attribute mark_debug of fifo_accept : signal is "true";
--attribute mark_debug of fifo_dvalid : signal is "true";
--attribute mark_debug of state : signal is "true";
--attribute mark_debug of fsm_in : signal is "true";
--attribute mark_debug of fifo_full : signal is "true";
--attribute mark_debug of fifo_dreq : signal is "true";
signal fifo_target_ts_en : std_logic;
signal fifo_target_ts : std_logic_vector(28 downto 0);
......
modules/wr_streamers/xtx_streamer.vhd
View file @ 34a55986
......@@ -208,12 +208,12 @@ architecture rtl of xtx_streamer is
signal link_ok_ref : std_logic;
attribute mark_debug : string;
--attribute mark_debug : string;
attribute mark_debug of link_ok_delay_cnt : signal is "true";
attribute mark_debug of link_ok_delay_expired_ref : signal is "true";
attribute mark_debug of link_ok_delay_expired : signal is "true";
attribute mark_debug of link_ok_ref : signal is "true";
--attribute mark_debug of link_ok_delay_cnt : signal is "true";
--attribute mark_debug of link_ok_delay_expired_ref : signal is "true";
--attribute mark_debug of link_ok_delay_expired : signal is "true";
--attribute mark_debug of link_ok_ref : signal is "true";
signal clk_data : std_logic;
......
modules/wr_streamers/xwr_streamers.vhd
View file @ 34a55986
......@@ -102,7 +102,9 @@ entity xwr_streamers is
-- shorten the duration of second to see TAI seconds for simulation only (i.e.
-- only if g_simulation = 1)
g_sim_cycle_counter_range : integer := 125000
g_sim_cycle_counter_range : integer := 125000;
g_with_dbg_word : boolean := TRUE
);
port (
......@@ -467,24 +469,27 @@ begin
-- word is of sufficient width
-------------------------------------------------------------------------------------------
start_bit <= from_wb.dbg_ctrl_start_byte_o & "000";
p_debug_mux: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dbg_word <= (others =>'0');
else
if(from_wb.dbg_ctrl_mux_o = '1') then --rx
if(rx_valid = '1') then
dbg_word <= f_dbg_word_starting_at_bit(rx_data,start_bit,g_rx_streamer_params.data_width);
end if;
else -- tx
if(tx_valid_i = '1') then
dbg_word <= f_dbg_word_starting_at_bit(tx_data_i,start_bit,g_tx_streamer_params.data_width);
gen_with_dbg_word: if g_with_dbg_word generate
p_debug_mux: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dbg_word <= (others =>'0');
else
if(from_wb.dbg_ctrl_mux_o = '1') then --rx
if(rx_valid = '1') then
dbg_word <= f_dbg_word_starting_at_bit(rx_data,start_bit,g_rx_streamer_params.data_width);
end if;
else -- tx
if(tx_valid_i = '1') then
dbg_word <= f_dbg_word_starting_at_bit(tx_data_i,start_bit,g_tx_streamer_params.data_width);
end if;
end if;
end if;
end if;
end if;
end process;
end process;
end generate gen_with_dbg_word;
------------------------------------------------------------------------------------------------------
--------------------------------- Assemble the final snmp/diag output --------------------------------
......
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