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White Rabbit core collection
Commits
1990656b
Commit
1990656b
authored
May 05, 2021
by
Grzegorz Daniluk
Browse files
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temp: comment stuff that makes vivado hierarchy solver unhappy
parent
2b7c7fb8
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4 changed files
with
1839 additions
and
1768 deletions
+1839
-1768
xwrc_board_common.vhd
board/common/xwrc_board_common.vhd
+75
-75
wr_gthe4_phy_family7_xilinx_ip.vhd
..._gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd
+74
-3
gtwizard_ultrascale_2_gtwizard_gthe4.v
...hy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v
+76
-76
gtwizard_ultrascale_2_gtwizard_top.v
..._phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v
+1614
-1614
No files found.
board/common/xwrc_board_common.vhd
View file @
1990656b
...
...
@@ -494,86 +494,86 @@ begin -- architecture struct
gen_wr_streamers
:
if
(
g_fabric_iface
=
STREAMERS
)
generate
cmp_xwr_streamers
:
xwr_streamers
generic
map
(
g_streamers_op_mode
=>
g_streamers_op_mode
,
g_tx_streamer_params
=>
g_tx_streamer_params
,
g_rx_streamer_params
=>
g_rx_streamer_params
,
g_simulation
=>
g_simulation
,
g_clk_ref_rate
=>
f_pick_clk_ref_rate
(
g_pcs_16bit
))
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
src_i
=>
wrf_snk_out
,
src_o
=>
wrf_snk_in
,
snk_i
=>
wrf_src_out
,
snk_o
=>
wrf_src_in
,
tx_data_i
=>
wrs_tx_data_i
,
tx_valid_i
=>
wrs_tx_valid_i
,
tx_dreq_o
=>
wrs_tx_dreq_o
,
tx_last_p1_i
=>
wrs_tx_last_i
,
tx_flush_p1_i
=>
wrs_tx_flush_i
,
rx_first_p1_o
=>
wrs_rx_first_o
,
rx_last_p1_o
=>
wrs_rx_last_o
,
rx_data_o
=>
wrs_rx_data_o
,
rx_valid_o
=>
wrs_rx_valid_o
,
rx_dreq_i
=>
wrs_rx_dreq_i
,
clk_ref_i
=>
clk_ref_i
,
tm_time_valid_i
=>
tm_time_valid
,
tm_tai_i
=>
tm_tai
,
tm_cycles_i
=>
tm_cycles
,
link_ok_i
=>
link_ok
,
wb_slave_i
=>
aux_master_out
,
wb_slave_o
=>
aux_master_in
,
snmp_array_o
=>
aux_diag_in
(
c_WR_STREAMERS_ARR_SIZE_OUT
-1
downto
0
),
snmp_array_i
=>
aux_diag_out
(
c_WR_STREAMERS_ARR_SIZE_IN
-1
downto
0
),
tx_streamer_cfg_i
=>
wrs_tx_cfg_i
,
rx_streamer_cfg_i
=>
wrs_rx_cfg_i
);
-- unused output ports
wrf_src_o
<=
c_dummy_snk_in
;
wrf_snk_o
<=
c_dummy_src_in
;
aux_master_o
<=
cc_dummy_master_out
;
wb_eth_master_o
<=
cc_dummy_master_out
;
aux_diag_in
(
c_diag_ro_size
-1
downto
c_WR_STREAMERS_ARR_SIZE_OUT
)
<=
aux_diag_i
;
aux_diag_o
<=
aux_diag_out
(
c_diag_rw_size
-1
downto
c_WR_STREAMERS_ARR_SIZE_IN
);
--GD
cmp_xwr_streamers : xwr_streamers
--GD
generic map (
--GD
g_streamers_op_mode => g_streamers_op_mode,
--GD
g_tx_streamer_params => g_tx_streamer_params,
--GD
g_rx_streamer_params => g_rx_streamer_params,
--GD
g_simulation => g_simulation,
--GD
g_clk_ref_rate => f_pick_clk_ref_rate(g_pcs_16bit))
--GD
port map (
--GD
clk_sys_i => clk_sys_i,
--GD
rst_n_i => rst_n_i,
--GD
src_i => wrf_snk_out,
--GD
src_o => wrf_snk_in,
--GD
snk_i => wrf_src_out,
--GD
snk_o => wrf_src_in,
--GD
tx_data_i => wrs_tx_data_i,
--GD
tx_valid_i => wrs_tx_valid_i,
--GD
tx_dreq_o => wrs_tx_dreq_o,
--GD
tx_last_p1_i => wrs_tx_last_i,
--GD
tx_flush_p1_i => wrs_tx_flush_i,
--GD
rx_first_p1_o => wrs_rx_first_o,
--GD
rx_last_p1_o => wrs_rx_last_o,
--GD
rx_data_o => wrs_rx_data_o,
--GD
rx_valid_o => wrs_rx_valid_o,
--GD
rx_dreq_i => wrs_rx_dreq_i,
--GD
clk_ref_i => clk_ref_i,
--GD
tm_time_valid_i => tm_time_valid,
--GD
tm_tai_i => tm_tai,
--GD
tm_cycles_i => tm_cycles,
--GD
link_ok_i => link_ok,
--GD
wb_slave_i => aux_master_out,
--GD
wb_slave_o => aux_master_in,
--GD
snmp_array_o => aux_diag_in(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0),
--GD
snmp_array_i => aux_diag_out(c_WR_STREAMERS_ARR_SIZE_IN-1 downto 0),
--GD
tx_streamer_cfg_i=> wrs_tx_cfg_i,
--GD
rx_streamer_cfg_i=> wrs_rx_cfg_i);
--GD
--GD
-- unused output ports
--GD
wrf_src_o <= c_dummy_snk_in;
--GD
wrf_snk_o <= c_dummy_src_in;
--GD
--GD
aux_master_o <= cc_dummy_master_out;
--GD
wb_eth_master_o <= cc_dummy_master_out;
--GD
--GD
aux_diag_in(c_diag_ro_size-1 downto c_WR_STREAMERS_ARR_SIZE_OUT) <= aux_diag_i;
--GD
aux_diag_o <= aux_diag_out(c_diag_rw_size-1 downto c_WR_STREAMERS_ARR_SIZE_IN);
end
generate
gen_wr_streamers
;
gen_etherbone
:
if
(
g_fabric_iface
=
ETHERBONE
)
generate
cmp_eb_ethernet_slave
:
eb_ethernet_slave
generic
map
(
g_sdb_address
=>
x"0000000000030000"
)
port
map
(
clk_i
=>
clk_sys_i
,
nRst_i
=>
aux_rst_n
,
src_o
=>
wrf_snk_in
,
src_i
=>
wrf_snk_out
,
snk_o
=>
wrf_src_in
,
snk_i
=>
wrf_src_out
,
cfg_slave_o
=>
aux_master_in
,
cfg_slave_i
=>
aux_master_out
,
master_o
=>
wb_eth_master_o
,
master_i
=>
wb_eth_master_i
);
-- unused output ports
wrf_src_o
<=
c_dummy_snk_in
;
wrf_snk_o
<=
c_dummy_src_in
;
wrs_tx_dreq_o
<=
'0'
;
wrs_rx_first_o
<=
'0'
;
wrs_rx_last_o
<=
'0'
;
wrs_rx_valid_o
<=
'0'
;
wrs_rx_data_o
<=
(
others
=>
'0'
);
aux_master_o
<=
cc_dummy_master_out
;
-- unused inputs to WR PTP core
aux_diag_in
<=
aux_diag_i
;
aux_diag_o
<=
aux_diag_out
;
--GD
cmp_eb_ethernet_slave : eb_ethernet_slave
--GD
generic map (
--GD
g_sdb_address => x"0000000000030000")
--GD
port map (
--GD
clk_i => clk_sys_i,
--GD
nRst_i => aux_rst_n,
--GD
src_o => wrf_snk_in,
--GD
src_i => wrf_snk_out,
--GD
snk_o => wrf_src_in,
--GD
snk_i => wrf_src_out,
--GD
cfg_slave_o => aux_master_in,
--GD
cfg_slave_i => aux_master_out,
--GD
master_o => wb_eth_master_o,
--GD
master_i => wb_eth_master_i);
--GD
--GD
-- unused output ports
--GD
wrf_src_o <= c_dummy_snk_in;
--GD
wrf_snk_o <= c_dummy_src_in;
--GD
--GD
wrs_tx_dreq_o <= '0';
--GD
wrs_rx_first_o <= '0';
--GD
wrs_rx_last_o <= '0';
--GD
wrs_rx_valid_o <= '0';
--GD
wrs_rx_data_o <= (others => '0');
--GD
--GD
aux_master_o <= cc_dummy_master_out;
--GD
--GD
-- unused inputs to WR PTP core
--GD
aux_diag_in <= aux_diag_i;
--GD
aux_diag_o <= aux_diag_out;
end
generate
gen_etherbone
;
...
...
platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd
View file @
1990656b
...
...
@@ -75,6 +75,76 @@ end wr_gthe4_phy_family7_xilinx_ip;
architecture
rtl
of
wr_gthe4_phy_family7_xilinx_ip
is
component
gtwizard_ultrascale_2
is
port
(
gthrxn_in
:
in
std_logic
;
gthrxp_in
:
in
std_logic
;
gthtxn_out
:
out
std_logic
;
gthtxp_out
:
out
std_logic
;
gtwiz_userclk_tx_reset_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_userclk_tx_usrclk_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_userclk_tx_usrclk2_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_userclk_tx_active_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_userclk_rx_reset_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_userclk_rx_usrclk_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_userclk_rx_usrclk2_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_userclk_rx_active_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_buffbypass_tx_reset_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_buffbypass_tx_start_user_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_buffbypass_tx_done_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_buffbypass_tx_error_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_buffbypass_rx_reset_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_buffbypass_rx_start_user_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_buffbypass_rx_done_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_buffbypass_rx_error_out
:
out
std_logic_vector
(
0
downto
0
);
drpaddr_in
:
in
std_logic_vector
(
9
downto
0
);
drpclk_in
:
in
std_logic
;
drpdi_in
:
in
std_logic_vector
(
15
downto
0
);
drpen_in
:
in
std_logic
;
drpwe_in
:
in
std_logic
;
eyescanreset_in
:
in
std_logic
;
gtrefclk0_in
:
in
std_logic
;
gtwiz_reset_clk_freerun_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_reset_all_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_reset_tx_pll_and_datapath_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_reset_tx_datapath_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_reset_rx_pll_and_datapath_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_reset_rx_datapath_in
:
in
std_logic_vector
(
0
downto
0
);
gtwiz_reset_rx_cdr_stable_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_reset_tx_done_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_reset_rx_done_out
:
out
std_logic_vector
(
0
downto
0
);
gtwiz_userdata_tx_in
:
in
std_logic_vector
(
15
downto
0
);
gtwiz_userdata_rx_out
:
out
std_logic_vector
(
15
downto
0
);
rx8b10ben_in
:
in
std_logic_vector
(
0
downto
0
);
rxcommadeten_in
:
in
std_logic_vector
(
0
downto
0
);
rxmcommaalignen_in
:
in
std_logic_vector
(
0
downto
0
);
rxpcommaalignen_in
:
in
std_logic_vector
(
0
downto
0
);
rxslide_in
:
in
std_logic_vector
(
0
downto
0
);
tx8b10ben_in
:
in
std_logic_vector
(
0
downto
0
);
txctrl0_in
:
in
std_logic_vector
(
15
downto
0
);
txctrl1_in
:
in
std_logic_vector
(
15
downto
0
);
txctrl2_in
:
in
std_logic_vector
(
7
downto
0
);
rxbyteisaligned_out
:
out
std_logic_vector
(
0
downto
0
);
rxbyterealign_out
:
out
std_logic
;
rxcommadet_out
:
out
std_logic_vector
(
0
downto
0
);
rxctrl0_out
:
out
std_logic_vector
(
15
downto
0
);
rxctrl1_out
:
out
std_logic_vector
(
15
downto
0
);
rxctrl2_out
:
out
std_logic_vector
(
7
downto
0
);
rxctrl3_out
:
out
std_logic_vector
(
7
downto
0
);
rxpmaresetdone_out
:
out
std_logic_vector
(
0
downto
0
);
txpmaresetdone_out
:
out
std_logic_vector
(
0
downto
0
);
rxlpmen_in
:
in
std_logic_vector
(
0
downto
0
);
rxrate_in
:
in
std_logic_vector
(
2
downto
0
);
txdiffctrl_in
:
in
std_logic_vector
(
4
downto
0
);
txpostcursor_in
:
in
std_logic_vector
(
4
downto
0
);
txprecursor_in
:
in
std_logic_vector
(
4
downto
0
)
);
end
component
gtwizard_ultrascale_2
;
signal
gtwiz_userclk_tx_reset_in
:
std_logic
;
-- signal gtwiz_userclk_tx_srcclk_out : std_logic;
-- signal gtwiz_userclk_tx_usrclk_out : std_logic;
...
...
@@ -240,18 +310,19 @@ begin
gtwiz_reset_all_in
<=
rst_i
;
U_gtwizard_gthe4
:
entity
work
.
gtwizard_ultrascale_2
-- U_gtwizard_gthe4 : entity work.gtwizard_ultrascale_2
U_gtwizard_gthe4
:
gtwizard_ultrascale_2
port
map
(
gthrxn_in
=>
pad_rxn_i
,
gthrxp_in
=>
pad_rxp_i
,
gthtxn_out
=>
pad_txn_o
,
gthtxp_out
=>
pad_txp_o
,
gtwiz_userclk_tx_reset_in
(
0
)
=>
gtwiz_userclk_tx_reset_in
,
-- gtwiz_userclk_tx_usrclk_out(0)
=> gtwiz_userclk_tx_usrclk_out
,
-- gtwiz_userclk_tx_usrclk_out(0)
=> open
,
gtwiz_userclk_tx_usrclk2_out
(
0
)
=>
tx_clk
,
gtwiz_userclk_tx_active_out
(
0
)
=>
gtwiz_userclk_tx_active_out
,
gtwiz_userclk_rx_reset_in
(
0
)
=>
gtwiz_userclk_rx_reset_in
,
--
gtwiz_userclk_rx_usrclk_out(0) => gtwiz_userclk_rx_usrclk_out
,
--
gtwiz_userclk_rx_usrclk_out(0) => open
,
gtwiz_userclk_rx_usrclk2_out
(
0
)
=>
rx_clk
,
gtwiz_userclk_rx_active_out
(
0
)
=>
gtwiz_userclk_rx_active_out
,
gtwiz_buffbypass_tx_reset_in
(
0
)
=>
gtwiz_buffbypass_tx_reset_in
,
...
...
platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v
View file @
1990656b
...
...
@@ -1150,7 +1150,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
for
(
cm
=
0
;
cm
<
`gtwizard_ultrascale_2_gtwizard_gthe4_MAX_NUM_COMMONS
;
cm
=
cm
+
1
)
begin
:
gen_common_container
if
(
P_COMMON_ENABLE
[
cm
]
==
1'b1
)
begin
:
gen_enabled_common
gtwizard_ultrascale_2_gthe4_common_wrapper
gthe4_common_wrapper_inst
(
/*
gtwizard_ultrascale_2_gthe4_common_wrapper gthe4_common_wrapper_inst (
.GTHE4_COMMON_BGBYPASSB (bgbypassb_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]),
.GTHE4_COMMON_BGMONITORENB (bgmonitorenb_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]),
.GTHE4_COMMON_BGPDB (bgpdb_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]),
...
...
@@ -1238,7 +1238,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
.GTHE4_COMMON_SDM1TESTDATA (sdm1testdata_int [f_ub_cm(15,(4*cm)+3) : f_lb_cm(15,4*cm)]),
.GTHE4_COMMON_TCONGPO (tcongpo_int [f_ub_cm(10,(4*cm)+3) : f_lb_cm(10,4*cm)]),
.GTHE4_COMMON_TCONRSVDOUT0 (tconrsvdout0_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)])
)
;
);
*/
end
end
...
...
@@ -2595,80 +2595,80 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
assign
drpen_ch_int
=
drpen_int
;
assign
drpwe_ch_int
=
drpwe_int
;
end
if
(
0
)
begin
:
gen_cpll_cal_gtye4
gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal
#(
.
C_SIM_CPLL_CAL_BYPASS
(
//pragma translate_off
C_SIM_CPLL_CAL_BYPASS
||
//pragma translate_on
1'b0
)
,
.
C_PCIE_ENABLE
(
C_PCIE_ENABLE
)
,
.
C_FREERUN_FREQUENCY
(
C_FREERUN_FREQUENCY
)
,
.
C_RX_PLL_TYPE
(
C_RX_PLL_TYPE
)
,
.
C_TX_PLL_TYPE
(
C_TX_PLL_TYPE
)
,
.
C_PCIE_CORECLK_FREQ
(
C_PCIE_CORECLK_FREQ
)
)
gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst
(
.
TXOUTCLK_PERIOD_IN
(
18'b0
)
,
.
WAIT_DEASSERT_CPLLPD_IN
(
16'b0
)
,
.
CNT_TOL_IN
(
18'b0
)
,
.
FREQ_COUNT_WINDOW_IN
(
16'b0
)
,
.
RESET_IN
(
1'b0
)
,
.
CLK_IN
(
1'b0
)
,
.
DRPRST_IN
(
1'b0
)
,
.
USER_TXOUTCLK_BUFG_CE_IN
(
1'b0
)
,
.
USER_TXOUTCLK_BUFG_CLR_IN
(
1'b0
)
,
.
USER_TXPROGDIVRESET_IN
(
1'b0
)
,
.
GTYE4_RXOUTCLK_IN
(
1'b0
)
,
.
GTYE4_RXPMARESETDONE_IN
(
1'b0
)
,
.
GTYE4_RXPRGDIVRESETDONE_IN
(
1'b0
)
,
.
USER_GTRXRESET_IN
(
1'b0
)
,
.
USER_RXCDRHOLD_IN
(
1'b0
)
,
.
USER_RXOUTCLK_BUFG_CE_IN
(
1'b0
)
,
.
USER_RXOUTCLK_BUFG_CLR_IN
(
1'b0
)
,
.
USER_RXPMARESET_IN
(
1'b0
)
,
.
USER_RXPROGDIVRESET_IN
(
1'b0
)
,
.
USER_RXPLLCLKSEL
(
2'b00
)
,
.
USER_TXPLLCLKSEL
(
2'b00
)
,
.
USER_RXOUTCLKSEL_IN
(
3'b010
)
,
.
GTYE4_GTRXRESET_OUT
()
,
.
GTYE4_RXCDRHOLD_OUT
()
,
.
GTYE4_RXPMARESET_OUT
()
,
.
GTYE4_RXPROGDIVRESET_OUT
()
,
.
USER_RXPMARESETDONE_OUT
()
,
.
USER_RXPRGDIVRESETDONE_OUT
()
,
.
GTYE4_RXOUTCLKSEL_OUT
()
,
.
USER_TXPRGDIVRESETDONE_OUT
()
,
.
USER_TXOUTCLKSEL_IN
(
3'b0
)
,
.
USER_CPLLLOCK_OUT
()
,
.
USER_CHANNEL_DRPADDR_IN
(
9'b0
)
,
.
USER_CHANNEL_DRPDI_IN
(
16'b0
)
,
.
USER_CHANNEL_DRPEN_IN
(
1'b0
)
,
.
USER_CHANNEL_DRPWE_IN
(
1'b0
)
,
.
USER_CHANNEL_DRPRDY_OUT
()
,
.
USER_CHANNEL_DRPDO_OUT
()
,
.
CPLL_CAL_FAIL
()
,
.
CPLL_CAL_DONE
()
,
.
DEBUG_OUT
()
,
.
CAL_FREQ_CNT
()
,
.
REPEAT_RESET_LIMIT
(
4'd15
)
,
.
GTYE4_TXOUTCLK_IN
(
1'b0
)
,
.
GTYE4_CPLLLOCK_IN
(
1'b0
)
,
.
GTYE4_CPLLRESET_OUT
()
,
.
GTYE4_CPLLPD_OUT
()
,
.
GTYE4_TXPROGDIVRESET_OUT
()
,
.
GTYE4_TXOUTCLKSEL_OUT
()
,
.
GTYE4_TXPRGDIVRESETDONE_IN
(
1'b0
)
,
.
GTYE4_CHANNEL_DRPADDR_OUT
()
,
.
GTYE4_CHANNEL_DRPDI_OUT
()
,
.
GTYE4_CHANNEL_DRPEN_OUT
()
,
.
GTYE4_CHANNEL_DRPWE_OUT
()
,
.
GTYE4_CHANNEL_DRPRDY_IN
(
1'b0
)
,
.
GTYE4_CHANNEL_DRPDO_IN
(
16'b0
)
)
;
end
//GD
if (0) begin : gen_cpll_cal_gtye4
//GD
//GD
gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal #(
//GD
.C_SIM_CPLL_CAL_BYPASS(
//GD
//pragma translate_off
//GD
C_SIM_CPLL_CAL_BYPASS ||
//GD
//pragma translate_on
//GD
1'b0
//GD
),
//GD
.C_PCIE_ENABLE(C_PCIE_ENABLE),
//GD
.C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
//GD
.C_RX_PLL_TYPE(C_RX_PLL_TYPE),
//GD
.C_TX_PLL_TYPE(C_TX_PLL_TYPE),
//GD
.C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ)
//GD
) gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst (
//GD
.TXOUTCLK_PERIOD_IN (18'b0),
//GD
.WAIT_DEASSERT_CPLLPD_IN (16'b0),
//GD
.CNT_TOL_IN (18'b0),
//GD
.FREQ_COUNT_WINDOW_IN (16'b0),
//GD
.RESET_IN (1'b0),
//GD
.CLK_IN (1'b0),
//GD
.DRPRST_IN (1'b0),
//GD
.USER_TXOUTCLK_BUFG_CE_IN (1'b0),
//GD
.USER_TXOUTCLK_BUFG_CLR_IN (1'b0),
//GD
.USER_TXPROGDIVRESET_IN (1'b0),
//GD
.GTYE4_RXOUTCLK_IN (1'b0),
//GD
.GTYE4_RXPMARESETDONE_IN (1'b0),
//GD
.GTYE4_RXPRGDIVRESETDONE_IN (1'b0),
//GD
.USER_GTRXRESET_IN (1'b0),
//GD
.USER_RXCDRHOLD_IN (1'b0),
//GD
.USER_RXOUTCLK_BUFG_CE_IN (1'b0),
//GD
.USER_RXOUTCLK_BUFG_CLR_IN (1'b0),
//GD
.USER_RXPMARESET_IN (1'b0),
//GD
.USER_RXPROGDIVRESET_IN (1'b0),
//GD
.USER_RXPLLCLKSEL (2'b00),
//GD
.USER_TXPLLCLKSEL (2'b00),
//GD
.USER_RXOUTCLKSEL_IN (3'b010),
//GD
.GTYE4_GTRXRESET_OUT (),
//GD
.GTYE4_RXCDRHOLD_OUT (),
//GD
.GTYE4_RXPMARESET_OUT (),
//GD
.GTYE4_RXPROGDIVRESET_OUT (),
//GD
.USER_RXPMARESETDONE_OUT (),
//GD
.USER_RXPRGDIVRESETDONE_OUT (),
//GD
.GTYE4_RXOUTCLKSEL_OUT (),
//GD
.USER_TXPRGDIVRESETDONE_OUT (),
//GD
.USER_TXOUTCLKSEL_IN (3'b0),
//GD
.USER_CPLLLOCK_OUT (),
//GD
.USER_CHANNEL_DRPADDR_IN (9'b0),
//GD
.USER_CHANNEL_DRPDI_IN (16'b0),
//GD
.USER_CHANNEL_DRPEN_IN (1'b0),
//GD
.USER_CHANNEL_DRPWE_IN (1'b0),
//GD
.USER_CHANNEL_DRPRDY_OUT (),
//GD
.USER_CHANNEL_DRPDO_OUT (),
//GD
.CPLL_CAL_FAIL (),
//GD
.CPLL_CAL_DONE (),
//GD
.DEBUG_OUT (),
//GD
.CAL_FREQ_CNT (),
//GD
.REPEAT_RESET_LIMIT (4'd15),
//GD
.GTYE4_TXOUTCLK_IN (1'b0),
//GD
.GTYE4_CPLLLOCK_IN (1'b0),
//GD
.GTYE4_CPLLRESET_OUT (),
//GD
.GTYE4_CPLLPD_OUT (),
//GD
.GTYE4_TXPROGDIVRESET_OUT (),
//GD
.GTYE4_TXOUTCLKSEL_OUT (),
//GD
.GTYE4_TXPRGDIVRESETDONE_IN (1'b0),
//GD
.GTYE4_CHANNEL_DRPADDR_OUT (),
//GD
.GTYE4_CHANNEL_DRPDI_OUT (),
//GD
.GTYE4_CHANNEL_DRPEN_OUT (),
//GD
.GTYE4_CHANNEL_DRPWE_OUT (),
//GD
.GTYE4_CHANNEL_DRPRDY_IN (1'b0),
//GD
.GTYE4_CHANNEL_DRPDO_IN (16'b0)
//GD
);
//GD
//GD
end
genvar
pwrgood_delay
;
for
(
pwrgood_delay
=
0
;
pwrgood_delay
<
`gtwizard_ultrascale_2_gtwizard_gthe4_N_CH
;
pwrgood_delay
=
pwrgood_delay
+
1
)
begin
:
gen_pwrgood_delay_inst
...
...
platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v
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