Merge remote-tracking branch 'origin/tom-wrpc-v5-diags-in-dpram' into wrpc-v5

aca968bc · Tristan Gingold · b8c08098 · d569b726 · aca968bc · aca968bc
Commit aca968bc authored Mar 22, 2022 by Tristan Gingold
26 changed files
--- a/modules/wr_endpoint/ep_packet_filter.vhd
+++ b/modules/wr_endpoint/ep_packet_filter.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2010-11-18
-- Last update: 2018-10-25
+-- Last update: 2022-02-02
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -165,6 +165,10 @@ architecture behavioral of ep_packet_filter is

  signal pfcr0_enable_rxclk : std_logic;

+  signal pclass_int : std_logic_vector(7 downto 0);
+  signal drop_int, done_int_sys   : std_logic;
+
+  
 begin  -- behavioral

  U_sync_pfcr0_enable : gc_sync_ffs
@@ -344,22 +348,39 @@ begin  -- behavioral
    if rising_edge(clk_rx_i) then
      if (rst_n_rx_i = '0' or snk_fab_i.sof = '1') then
        done_int <= '0';
-        drop_o   <= '0';
+        drop_int  <= '0';
      else
        if(pfcr0_enable_rxclk = '0') then
          done_int <= '0';
-          drop_o   <= '0';
-          pclass_o <= (others => '0');
+          drop_int   <= '0';
+          pclass_int <= (others => '0');
        elsif( (stage3 = '1' and insn_d.fin = '1') or
               ((snk_fab_i.error = '1' or snk_fab_i.eof = '1') and done_int = '0') ) then
          done_int <= '1';
-          pclass_o <= regs(31 downto 24);
-          drop_o   <= regs(23);
+          pclass_int <= regs(31 downto 24);
+          drop_int   <= regs(23);
        end if;
      end if;
    end if;
  end process;

+  p_out_status : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(done_int_sys = '1') then
+        drop_o <= drop_int;
+        pclass_o <= pclass_int;
+        done_o <= '1';
+      else
+        done_o <= '0';
+      end if;
+      
+    end if;
+  end process;
+  
+  
+  
+
  U_Sync_Done : gc_pulse_synchronizer2
    port map (
      clk_in_i    => clk_rx_i,
@@ -367,6 +388,6 @@ begin  -- behavioral
      clk_out_i   => clk_sys_i,
      rst_out_n_i => rst_n_sys_i,
      d_p_i       => done_int,
-      q_p_o       => done_o);
+      q_p_o       => done_int_sys);

 end behavioral;
--- a/modules/wr_streamers/streamers_pkg.vhd
+++ b/modules/wr_streamers/streamers_pkg.vhd
@@ -335,7 +335,8 @@ package streamers_pkg is
    g_slave_mode               : t_wishbone_interface_mode      := CLASSIC;
    g_slave_granularity        : t_wishbone_address_granularity := BYTE;
    g_simulation               : integer := 0;
-    g_sim_cycle_counter_range  : integer := 125000
+    g_sim_cycle_counter_range  : integer := 125000;
+    g_with_dbg_word : boolean := TRUE
    );

  port (

--- a/modules/wr_streamers/xrx_streamer.vhd
+++ b/modules/wr_streamers/xrx_streamer.vhd
@@ -186,14 +186,14 @@ architecture rtl of xrx_streamer is
  signal fifo_sync, fifo_last, frames_lost, blocks_lost      : std_logic;
  signal fifo_dout, fifo_din                                 : std_logic_vector(g_data_width + 1 + 28 + 1 downto 0);

-  attribute mark_debug                : string;
-  attribute mark_debug of fifo_drop   : signal is "true";
-  attribute mark_debug of fifo_accept : signal is "true";
-  attribute mark_debug of fifo_dvalid : signal is "true";
-  attribute mark_debug of state       : signal is "true";
-  attribute mark_debug of fsm_in      : signal is "true";
-  attribute mark_debug of fifo_full   : signal is "true";
-  attribute mark_debug of fifo_dreq   : signal is "true";
+  --attribute mark_debug                : string;
+  --attribute mark_debug of fifo_drop   : signal is "true";
+  --attribute mark_debug of fifo_accept : signal is "true";
+  --attribute mark_debug of fifo_dvalid : signal is "true";
+  --attribute mark_debug of state       : signal is "true";
+  --attribute mark_debug of fsm_in      : signal is "true";
+  --attribute mark_debug of fifo_full   : signal is "true";
+  --attribute mark_debug of fifo_dreq   : signal is "true";

  signal fifo_target_ts_en : std_logic;
  signal fifo_target_ts    : std_logic_vector(28 downto 0);

--- a/modules/wr_streamers/xtx_streamer.vhd
+++ b/modules/wr_streamers/xtx_streamer.vhd
@@ -208,12 +208,12 @@ architecture rtl of xtx_streamer is
  signal link_ok_ref : std_logic;


-  attribute mark_debug : string;
+  --attribute mark_debug : string;

-  attribute mark_debug of link_ok_delay_cnt         : signal is "true";
-  attribute mark_debug of link_ok_delay_expired_ref : signal is "true";
-  attribute mark_debug of link_ok_delay_expired     : signal is "true";
-  attribute mark_debug of link_ok_ref               : signal is "true";
+  --attribute mark_debug of link_ok_delay_cnt         : signal is "true";
+  --attribute mark_debug of link_ok_delay_expired_ref : signal is "true";
+  --attribute mark_debug of link_ok_delay_expired     : signal is "true";
+  --attribute mark_debug of link_ok_ref               : signal is "true";


  signal clk_data  : std_logic;

--- a/modules/wr_streamers/xwr_streamers.vhd
+++ b/modules/wr_streamers/xwr_streamers.vhd
@@ -102,7 +102,9 @@ entity xwr_streamers is

    -- shorten the duration of second to see TAI seconds for simulation only (i.e.
    -- only if g_simulation = 1)
-    g_sim_cycle_counter_range  : integer := 125000
+    g_sim_cycle_counter_range  : integer := 125000;
+
+    g_with_dbg_word : boolean := TRUE
    );

  port (
@@ -467,24 +469,27 @@ begin
  --   word is of sufficient width
  -------------------------------------------------------------------------------------------
  start_bit <= from_wb.dbg_ctrl_start_byte_o & "000";
-  p_debug_mux: process(clk_sys_i)
-  begin
-    if rising_edge(clk_sys_i) then
-      if rst_n_i = '0' then
-        dbg_word <= (others =>'0');
-      else
-        if(from_wb.dbg_ctrl_mux_o = '1') then --rx
-          if(rx_valid = '1') then
-            dbg_word <= f_dbg_word_starting_at_bit(rx_data,start_bit,g_rx_streamer_params.data_width);
-          end if;
-        else -- tx
-          if(tx_valid_i = '1') then
-            dbg_word <= f_dbg_word_starting_at_bit(tx_data_i,start_bit,g_tx_streamer_params.data_width);
+
+  gen_with_dbg_word: if g_with_dbg_word generate
+    p_debug_mux: process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          dbg_word <= (others =>'0');
+        else
+          if(from_wb.dbg_ctrl_mux_o = '1') then --rx
+            if(rx_valid = '1') then
+              dbg_word <= f_dbg_word_starting_at_bit(rx_data,start_bit,g_rx_streamer_params.data_width);
+            end if;
+          else -- tx
+            if(tx_valid_i = '1') then
+              dbg_word <= f_dbg_word_starting_at_bit(tx_data_i,start_bit,g_tx_streamer_params.data_width);
+            end if;
          end if;
        end if;
      end if;
-    end if;
-  end process;
+    end process;
+  end generate gen_with_dbg_word;

  ------------------------------------------------------------------------------------------------------
  --------------------------------- Assemble the final snmp/diag output --------------------------------

--- a/modules/wrc_core/Manifest.py
+++ b/modules/wrc_core/Manifest.py
@@ -4,7 +4,5 @@ files = [ "xwr_core.vhd",
          "wrc_periph.vhd",
          "wrc_syscon_wb.vhd",
          "wrc_syscon_pkg.vhd",
-          "wrc_diags_wb.vhd",
-          "wrc_diags_pkg.vhd",
-          "xwrc_diags_wb.vhd"];
+          "wrc_diags_dpram.vhd"];

--- a/modules/wrc_core/build_wb.sh
+++ b/modules/wrc_core/build_wb.sh
@@ -2,4 +2,4 @@

 mkdir -p doc
 wbgen2 -D ./doc/wrc_syscon.html -p wrc_syscon_pkg.vhd -H record -V wrc_syscon_wb.vhd -C wrc_syscon_regs.h --cstyle defines --lang vhdl -K ../../sim/wrc_syscon_regs.vh wrc_syscon_wb.wb
-wbgen2 -D ./doc/wrc_diags.html -p wrc_diags_pkg.vhd -H record -V wrc_diags_wb.vhd -C wrc_diags_regs.h --cstyle struct --lang vhdl -K ../../sim/wrc_diags_regs.vh wrc_diags_wb.wb
+wbgen2 -D ./doc/wrc_diags.html -p wrc_diags_pkg.vhd -H record -V wrc_diags_wb.vhd -C wrc_diags_regs.h --cstyle defines --lang vhdl -K ../../sim/wrc_diags_regs.vh wrc_diags_wb.wb
--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-02
-- Last update: 2021-01-15
+-- Last update: 2022-01-17
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -92,6 +92,7 @@ entity wr_core is
    g_tx_runt_padding           : boolean                        := true;
    g_dpram_initf               : string                         := "default";
    g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+    g_use_platform_specific_dpram        : boolean := FALSE;
    g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
    g_address_granularity       : t_wishbone_address_granularity := BYTE;
    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
@@ -103,7 +104,8 @@ entity wr_core is
    g_diag_id                   : integer                        := 0;
    g_diag_ver                  : integer                        := 0;
    g_diag_ro_size              : integer                        := 0;
-    g_diag_rw_size              : integer                        := 0);
+    g_diag_rw_size              : integer                        := 0
+    );
  port(
    ---------------------------------------------------------------------------
    -- Clocks/resets
@@ -425,15 +427,15 @@ architecture struct of wr_core is
  -----------------------------------------------------------------------------
  --WB Peripherials
  -----------------------------------------------------------------------------
-  signal periph_slave_i : t_wishbone_slave_in_array(0 to 3);
-  signal periph_slave_o : t_wishbone_slave_out_array(0 to 3);
+  signal periph_slave_i : t_wishbone_slave_in_array(0 to 4);
+  signal periph_slave_o : t_wishbone_slave_out_array(0 to 4);
  signal sysc_in_regs   : t_sysc_in_registers;
  signal sysc_out_regs  : t_sysc_out_registers;

  -----------------------------------------------------------------------------
  --WB Secondary Crossbar
  -----------------------------------------------------------------------------
-  constant c_secbar_layout : t_sdb_record_array(8 downto 0) :=
+  constant c_secbar_layout : t_sdb_record_array(9 downto 0) :=
    (0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
     1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
     2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
@@ -441,16 +443,19 @@ architecture struct of wr_core is
     4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"),  -- Syscon
     5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"),  -- UART
     6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"),  -- 1-Wire
-     7 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000800"),  -- WRPC diag registers
-     8 => f_sdb_embed_device(g_aux_sdb,         x"00008000")   -- aux WB bus
+     -- WRPC diag registers (user access)
+     7 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000800"),
+     -- WRPC diag registers (WRC private)
+     8 => f_sdb_embed_device(c_wrc_periph5_sdb, x"00000900"),
+     9 => f_sdb_embed_device(g_aux_sdb,         x"00008000")   -- aux WB bus
     );

  constant c_secbar_sdb_address : t_wishbone_address := x"00000C00";
  constant c_secbar_bridge_sdb  : t_sdb_bridge       :=
    f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);

-  signal secbar_master_i : t_wishbone_master_in_array(8 downto 0);
-  signal secbar_master_o : t_wishbone_master_out_array(8 downto 0);
+  signal secbar_master_i : t_wishbone_master_in_array(9 downto 0);
+  signal secbar_master_o : t_wishbone_master_out_array(9 downto 0);



@@ -485,13 +490,13 @@ architecture struct of wr_core is
  signal cbar_master_i : t_wishbone_master_in_array(1 downto 0);
  signal cbar_master_o : t_wishbone_master_out_array(1 downto 0);

-  attribute mark_debug : string;
-  attribute mark_debug of cbar_master_o : signal is "true";
-  attribute mark_debug of cbar_master_i : signal is "true";
-  attribute mark_debug of cbar_slave_o : signal is "true";
-  attribute mark_debug of cbar_slave_i : signal is "true";
-  attribute mark_debug of secbar_master_o : signal is "true";
-  attribute mark_debug of secbar_master_i : signal is "true";
+  --attribute mark_debug : string;
+  --attribute mark_debug of cbar_master_o : signal is "true";
+  --attribute mark_debug of cbar_master_i : signal is "true";
+  --attribute mark_debug of cbar_slave_o : signal is "true";
+  --attribute mark_debug of cbar_slave_i : signal is "true";
+  --attribute mark_debug of secbar_master_o : signal is "true";
+  --attribute mark_debug of secbar_master_i : signal is "true";


  -----------------------------------------------------------------------------
@@ -907,25 +912,29 @@ begin
  -----------------------------------------------------------------------------
  -- Dual-port RAM
  -----------------------------------------------------------------------------
-  DPRAM : xwb_dpram
-    generic map(
-      g_size                  => g_dpram_size,
-      g_init_file             => f_choose_lm32_firmware_file,
-      g_must_have_init_file   => f_check_if_lm32_firmware_necessary,
-      g_slave1_interface_mode => PIPELINED,
-      g_slave2_interface_mode => PIPELINED,
-      g_slave1_granularity    => BYTE,
-      g_slave2_granularity    => WORD)
-    port map(
-      clk_sys_i => clk_sys_i,
-      rst_n_i   => rst_n_i,
-
-      slave1_i => cbar_master_o(0),
-      slave1_o => cbar_master_i(0),
-      slave2_i => dpram_wbb_i,
-      slave2_o => open
-      );

+  gen_use_generic_dpram : if g_use_platform_specific_dpram = false generate
+    DPRAM : xwb_dpram
+      generic map(
+        g_size                  => g_dpram_size,
+        g_init_file             => f_choose_lm32_firmware_file,
+        g_must_have_init_file   => f_check_if_lm32_firmware_necessary,
+        g_slave1_interface_mode => PIPELINED,
+        g_slave2_interface_mode => PIPELINED,
+        g_slave1_granularity    => BYTE,
+        g_slave2_granularity    => WORD)
+      port map(
+        clk_sys_i => clk_sys_i,
+        rst_n_i   => rst_n_i,
+
+        slave1_i => cbar_master_o(0),
+        slave1_o => cbar_master_i(0),
+        slave2_i => dpram_wbb_i,
+        slave2_o => open
+        );
+  end generate gen_use_generic_dpram;
+  
+  
  dpram_wbb_i.cyc <= '0';
  dpram_wbb_i.stb <= '0';
  dpram_wbb_i.adr <= (others=>'0');
@@ -933,6 +942,23 @@ begin
  dpram_wbb_i.we  <= '0'; --mnic_mem_wr_o;
  dpram_wbb_i.dat <= (others=>'0'); --mnic_mem_data_o;

+  gen_use_platform_dpram : if g_use_platform_specific_dpram = true generate
+    DPRAM : wrc_platform_dpram
+      generic map(
+        g_size                  => g_dpram_size,
+        g_init_file             => f_choose_lm32_firmware_file,
+        g_must_have_init_file   => f_check_if_lm32_firmware_necessary)
+      port map(
+        clk_sys_i => clk_sys_i,
+        rst_n_i   => rst_n_i,
+
+        slave1_i => cbar_master_o(0),
+        slave1_o => cbar_master_i(0),
+        slave2_i => dpram_wbb_i,
+        slave2_o => open
+        );
+  end generate gen_use_platform_dpram;
+  
  -----------------------------------------------------------------------------
  -- WB Peripherials
  -----------------------------------------------------------------------------
@@ -1093,7 +1119,7 @@ begin
    generic map(
      g_verbose     => g_verbose,
      g_num_masters => 1,
-      g_num_slaves  => 9,
+      g_num_slaves  => 10,
      g_registered  => true,
      g_wraparound  => true,
      g_layout      => c_secbar_layout,
@@ -1123,24 +1149,27 @@ begin
  secbar_master_i(5) <= periph_slave_o(1);
  secbar_master_i(6) <= periph_slave_o(2);
  secbar_master_i(7) <= periph_slave_o(3);
+  secbar_master_i(8) <= periph_slave_o(4);
+
  periph_slave_i(0)  <= secbar_master_o(4);
  periph_slave_i(1)  <= secbar_master_o(5);
  periph_slave_i(2)  <= secbar_master_o(6);
  periph_slave_i(3)  <= secbar_master_o(7);
+  periph_slave_i(4)  <= secbar_master_o(8);


-  aux_adr_o <= secbar_master_o(8).adr;
-  aux_dat_o <= secbar_master_o(8).dat;
-  aux_sel_o <= secbar_master_o(8).sel;
-  aux_cyc_o <= secbar_master_o(8).cyc;
-  aux_stb_o <= secbar_master_o(8).stb;
-  aux_we_o  <= secbar_master_o(8).we;
+  aux_adr_o <= secbar_master_o(9).adr;
+  aux_dat_o <= secbar_master_o(9).dat;
+  aux_sel_o <= secbar_master_o(9).sel;
+  aux_cyc_o <= secbar_master_o(9).cyc;
+  aux_stb_o <= secbar_master_o(9).stb;
+  aux_we_o  <= secbar_master_o(9).we;

-  secbar_master_i(8).dat   <= aux_dat_i;
-  secbar_master_i(8).ack   <= aux_ack_i;
-  secbar_master_i(8).stall <= aux_stall_i;
-  secbar_master_i(8).err   <= '0';
-  secbar_master_i(8).rty   <= '0';
+  secbar_master_i(9).dat   <= aux_dat_i;
+  secbar_master_i(9).ack   <= aux_ack_i;
+  secbar_master_i(9).stall <= aux_stall_i;
+  secbar_master_i(9).err   <= '0';
+  secbar_master_i(9).rty   <= '0';


  -----------------------------------------------------------------------------

--- a/modules/wrc_core/wrc_diags_dpram.vhd
+++ b/modules/wrc_core/wrc_diags_dpram.vhd
+-------------------------------------------------------------------------------
+-- Title      : Dual-port RAM for WR core
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : wrc_dpram.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN
+-- Created    : 2011-02-15
+-- Last update: 2021-06-19
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- Dual port RAM with wishbone interface
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-02-15  1.0      greg.d          Created
+-- 2011-06-09  1.01     twlostow        Removed unnecessary generics
+-- 2011-21-09  1.02     twlostow        Struct-ized version
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wrc_diags_dpram is
+  generic(
+    g_size                  : natural := 256
+    );
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- R/O slave (except the 1st, control word)
+    slave_user_i : in  t_wishbone_slave_in;
+    slave_user_o : out t_wishbone_slave_out;
+    -- R/W slave
+    slave_wrc_i : in  t_wishbone_slave_in;
+    slave_wrc_o : out t_wishbone_slave_out
+    );
+end wrc_diags_dpram;
+
+architecture struct of wrc_diags_dpram is
+  signal s_is_control_word : std_logic;
+  signal s_we_wrc  : std_logic;
+  signal s_we_user : std_logic;
+begin
+
+  U_DPRAM : generic_dpram
+    generic map(
+      -- standard parameters
+      g_data_width               => 32,
+      g_size                     => g_size,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "dont_care",
+      g_init_file                => "",
+      g_dual_clock               => false
+      )
+    port map(
+      rst_n_i => rst_n_i,
+      -- Port A
+      clka_i  => clk_sys_i,
+      wea_i   => s_we_wrc,
+      aa_i    => slave_wrc_i.adr(f_log2_size(g_size)+1 downto 2),
+      da_i    => slave_wrc_i.dat,
+      qa_o    => slave_wrc_o.dat,
+      -- Port B
+      clkb_i  => clk_sys_i,
+      web_i   => s_we_user,
+      ab_i    => slave_user_i.adr(f_log2_size(g_size)+1 downto 2),
+      db_i    => slave_user_i.dat,
+      qb_o    => slave_user_o.dat
+      );
+
+
+  s_is_control_word <= '1' when unsigned(slave_user_i.adr(f_log2_size(g_size)+1 downto 2) ) = 0 else '0';
+
+  s_we_user <= s_is_control_word and slave_user_i.we and slave_user_i.stb and slave_user_i.cyc;
+  s_we_wrc <= slave_wrc_i.we and slave_wrc_i.stb and slave_wrc_i.cyc;
+
+  process(clk_sys_i)
+  begin
+    if(rising_edge(clk_sys_i)) then
+      if(rst_n_i = '0') then
+        slave_user_o.ack <= '0';
+        slave_wrc_o.ack <= '0';
+      else
+        slave_user_o.ack <= slave_user_i.cyc and slave_user_i.stb;
+        slave_wrc_o.ack <= slave_wrc_i.cyc and slave_wrc_i.stb;
+      end if;
+    end if;
+  end process;
+
+  slave_wrc_o.stall <= '0';
+  slave_user_o.stall <= '0';
+  slave_wrc_o.err   <= '0';
+  slave_user_o.err   <= '0';
+  slave_wrc_o.rty   <= '0';
+  slave_user_o.rty   <= '0';
+  
+end struct;
+
--- a/modules/wrc_core/wrc_diags_pkg.vhd
+++ b/modules/wrc_core/wrc_diags_pkg.vhd
---------------------------------------------------------------------------------------
-- Title          : Wishbone slave core for WR Core Diagnostics
---------------------------------------------------------------------------------------
-- File           : wrc_diags_pkg.vhd
-- Author         : auto-generated by wbgen2 from wrc_diags_wb.wb
-- Created        : Mon Nov  2 16:06:06 2020
-- Version        : 0x00000001
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-package wrc_diags_wbgen2_pkg is
-  
-  
-  -- Input registers (user design -> WB slave)
-  
-  type t_wrc_diags_in_registers is record
-    ctrl_data_valid_i                        : std_logic;
-    wdiag_sstat_wr_mode_i                    : std_logic;
-    wdiag_sstat_servostate_i                 : std_logic_vector(3 downto 0);
-    wdiag_pstat_link_i                       : std_logic;
-    wdiag_pstat_locked_i                     : std_logic;
-    wdiag_ptpstat_ptpstate_i                 : std_logic_vector(7 downto 0);
-    wdiag_astat_aux_i                        : std_logic_vector(7 downto 0);
-    wdiag_txfcnt_i                           : std_logic_vector(31 downto 0);
-    wdiag_rxfcnt_i                           : std_logic_vector(31 downto 0);
-    wdiag_sec_msb_i                          : std_logic_vector(31 downto 0);
-    wdiag_sec_lsb_i                          : std_logic_vector(31 downto 0);
-    wdiag_ns_i                               : std_logic_vector(31 downto 0);
-    wdiag_mu_msb_i                           : std_logic_vector(31 downto 0);
-    wdiag_mu_lsb_i                           : std_logic_vector(31 downto 0);
-    wdiag_dms_msb_i                          : std_logic_vector(31 downto 0);
-    wdiag_dms_lsb_i                          : std_logic_vector(31 downto 0);
-    wdiag_asym_i                             : std_logic_vector(31 downto 0);
-    wdiag_cko_i                              : std_logic_vector(31 downto 0);
-    wdiag_setp_i                             : std_logic_vector(31 downto 0);
-    wdiag_ucnt_i                             : std_logic_vector(31 downto 0);
-    wdiag_temp_i                             : std_logic_vector(31 downto 0);
-    end record;
-  
-  constant c_wrc_diags_in_registers_init_value: t_wrc_diags_in_registers := (
-    ctrl_data_valid_i => '0',
-    wdiag_sstat_wr_mode_i => '0',
-    wdiag_sstat_servostate_i => (others => '0'),
-    wdiag_pstat_link_i => '0',
-    wdiag_pstat_locked_i => '0',
-    wdiag_ptpstat_ptpstate_i => (others => '0'),
-    wdiag_astat_aux_i => (others => '0'),
-    wdiag_txfcnt_i => (others => '0'),
-    wdiag_rxfcnt_i => (others => '0'),
-    wdiag_sec_msb_i => (others => '0'),
-    wdiag_sec_lsb_i => (others => '0'),
-    wdiag_ns_i => (others => '0'),
-    wdiag_mu_msb_i => (others => '0'),
-    wdiag_mu_lsb_i => (others => '0'),
-    wdiag_dms_msb_i => (others => '0'),
-    wdiag_dms_lsb_i => (others => '0'),
-    wdiag_asym_i => (others => '0'),
-    wdiag_cko_i => (others => '0'),
-    wdiag_setp_i => (others => '0'),
-    wdiag_ucnt_i => (others => '0'),
-    wdiag_temp_i => (others => '0')
-    );
-    
-    -- Output registers (WB slave -> user design)
-    
-    type t_wrc_diags_out_registers is record
-      ver_id_o                                 : std_logic_vector(31 downto 0);
-      ctrl_data_snapshot_o                     : std_logic;
-      end record;
-    
-    constant c_wrc_diags_out_registers_init_value: t_wrc_diags_out_registers := (
-      ver_id_o => (others => '0'),
-      ctrl_data_snapshot_o => '0'
-      );
-    function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers;
-    function f_x_to_zero (x:std_logic) return std_logic;
-    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
-end package;
-
-package body wrc_diags_wbgen2_pkg is
-function f_x_to_zero (x:std_logic) return std_logic is
-begin
-if x = '1' then
-return '1';
-else
-return '0';
-end if;
-end function;
-function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
-variable tmp: std_logic_vector(x'length-1 downto 0);
-begin
-for i in 0 to x'length-1 loop
-if(x(i) = '1') then
-tmp(i):= '1';
-else
-tmp(i):= '0';
-end if; 
-end loop; 
-return tmp;
-end function;
-function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers is
-variable tmp: t_wrc_diags_in_registers;
-begin
-tmp.ctrl_data_valid_i := f_x_to_zero(left.ctrl_data_valid_i) or f_x_to_zero(right.ctrl_data_valid_i);
-tmp.wdiag_sstat_wr_mode_i := f_x_to_zero(left.wdiag_sstat_wr_mode_i) or f_x_to_zero(right.wdiag_sstat_wr_mode_i);
-tmp.wdiag_sstat_servostate_i := f_x_to_zero(left.wdiag_sstat_servostate_i) or f_x_to_zero(right.wdiag_sstat_servostate_i);
-tmp.wdiag_pstat_link_i := f_x_to_zero(left.wdiag_pstat_link_i) or f_x_to_zero(right.wdiag_pstat_link_i);
-tmp.wdiag_pstat_locked_i := f_x_to_zero(left.wdiag_pstat_locked_i) or f_x_to_zero(right.wdiag_pstat_locked_i);
-tmp.wdiag_ptpstat_ptpstate_i := f_x_to_zero(left.wdiag_ptpstat_ptpstate_i) or f_x_to_zero(right.wdiag_ptpstat_ptpstate_i);
-tmp.wdiag_astat_aux_i := f_x_to_zero(left.wdiag_astat_aux_i) or f_x_to_zero(right.wdiag_astat_aux_i);
-tmp.wdiag_txfcnt_i := f_x_to_zero(left.wdiag_txfcnt_i) or f_x_to_zero(right.wdiag_txfcnt_i);
-tmp.wdiag_rxfcnt_i := f_x_to_zero(left.wdiag_rxfcnt_i) or f_x_to_zero(right.wdiag_rxfcnt_i);
-tmp.wdiag_sec_msb_i := f_x_to_zero(left.wdiag_sec_msb_i) or f_x_to_zero(right.wdiag_sec_msb_i);
-tmp.wdiag_sec_lsb_i := f_x_to_zero(left.wdiag_sec_lsb_i) or f_x_to_zero(right.wdiag_sec_lsb_i);
-tmp.wdiag_ns_i := f_x_to_zero(left.wdiag_ns_i) or f_x_to_zero(right.wdiag_ns_i);
-tmp.wdiag_mu_msb_i := f_x_to_zero(left.wdiag_mu_msb_i) or f_x_to_zero(right.wdiag_mu_msb_i);
-tmp.wdiag_mu_lsb_i := f_x_to_zero(left.wdiag_mu_lsb_i) or f_x_to_zero(right.wdiag_mu_lsb_i);
-tmp.wdiag_dms_msb_i := f_x_to_zero(left.wdiag_dms_msb_i) or f_x_to_zero(right.wdiag_dms_msb_i);
-tmp.wdiag_dms_lsb_i := f_x_to_zero(left.wdiag_dms_lsb_i) or f_x_to_zero(right.wdiag_dms_lsb_i);
-tmp.wdiag_asym_i := f_x_to_zero(left.wdiag_asym_i) or f_x_to_zero(right.wdiag_asym_i);
-tmp.wdiag_cko_i := f_x_to_zero(left.wdiag_cko_i) or f_x_to_zero(right.wdiag_cko_i);
-tmp.wdiag_setp_i := f_x_to_zero(left.wdiag_setp_i) or f_x_to_zero(right.wdiag_setp_i);
-tmp.wdiag_ucnt_i := f_x_to_zero(left.wdiag_ucnt_i) or f_x_to_zero(right.wdiag_ucnt_i);
-tmp.wdiag_temp_i := f_x_to_zero(left.wdiag_temp_i) or f_x_to_zero(right.wdiag_temp_i);
-return tmp;
-end function;
-end package body;
--- a/modules/wrc_core/wrc_diags_regs.cheby
+++ b/modules/wrc_core/wrc_diags_regs.cheby
+memory-map:
+  name: wrc_diags
+  description: WR Core Diagnostics
+  comment: Diagnostics information accessible via WR
+  bus: wb-32-be
+  x-wbgen:
+    hdl_entity: wrc_diags_wb
+    version: 1
+  schema-version:
+    core: 2.0.0
+    x-conversions: 1.0.0
+    x-driver-edge: 1.0.0
+    x-enums: 1.0.0
+    x-fesa: 2.0.0
+    x-gena: 2.0.0
+    x-hdl: 1.0.0
+    x-map-info: 1.0.0
+    x-wbgen: 1.0.0
+  children:
+  - reg:
+      name: VER
+      description: Version register
+      width: 32
+      access: rw
+      address: 0x0
+      children:
+      - field:
+          name: ID
+          description: Version identifier
+          range: 31-0
+          preset: 0x1
+          x-wbgen:
+            access_bus: READ_WRITE
+            access_dev: READ_ONLY
+            type: SLV
+  - reg:
+      name: CTRL
+      description: Ctrl
+      width: 32
+      access: rw
+      address: 0x4
+      children:
+      - field:
+          name: DATA_VALID
+          description: WR DIAG data valid
+          comment: '0: valid\n                     1:transcient'
+          range: 0
+          x-wbgen:
+            access_bus: READ_ONLY
+            access_dev: WRITE_ONLY
+            type: BIT
+      - field:
+          name: DATA_SNAPSHOT
+          description: WR DIAG data snapshot
+          comment: '1: snapshot data (data in registers will not change aveter VALID becomes true)'
+          range: 8
+          x-wbgen:
+            access_bus: READ_WRITE
+            access_dev: READ_ONLY
+            type: BIT
+  - reg:
+      name: WDIAG_SSTAT
+      description: 'WRPC Diag: servo status'
+      width: 32
+      access: ro
+      address: 0x8
+      children:
+      - field:
+          name: wr_mode
+          description: WR valid
+          comment: '0: not valid\n                     1:valid'
+          range: 0
+          x-wbgen:
+            access_bus: READ_ONLY
+            access_dev: WRITE_ONLY
+            type: BIT
+      - field:
+          name: servostate
+          description: Servo State
+          comment: '0: Uninitialized\n                     1: SYNC_NSEC\n                     2: SYNC_TAI\n                     3: SYNC_PHASE\n                     4: TRACK_PHASE\n                     5: WAIT_OFFSET_STABLE'
+          range: 11-8
+          x-wbgen:
+            access_bus: READ_ONLY
+            access_dev: WRITE_ONLY
+            type: SLV
+  - reg:
+      name: WDIAG_PSTAT
+      description: 'WRPC Diag: Port status'
+      width: 32
+      access: ro
+      address: 0xc
+      children:
+      - field:
+          name: link
+          description: Link Status
+          comment: '0: link down\n                     1: link up'
+          range: 0
+          x-wbgen:
+            access_bus: READ_ONLY
+            access_dev: WRITE_ONLY
+            type: BIT
+      - field:
+          name: locked
+          description: PLL Locked
+          comment: '0: not locked\n                     1: locked'
+          range: 1
+          x-wbgen:
+            access_bus: READ_ONLY
+            access_dev: WRITE_ONLY
+            type: BIT
+  - reg:
+      name: WDIAG_PTPSTAT
+      description: 'WRPC Diag: PTP state'
+      width: 32
+      access: ro
+      address: 0x10
+      children:
+      - field:
+          name: ptpstate
+          description: PTP State
+          comment: '0: NONE\n                     1: PPS_INITIALIZING\n                     2: PPS_FAULTY\n                     3: disabled\n                     4: PPS_LISTENING\n                     5: PPS_PRE_MASTER\n                     6: PPS_MASTER\n                     7: PPS_PASSIVE\n                     8: PPS_UNCALIBRATED\n                     9: PPS_SLAVE\n                     100-116: WR STATES\n                     see: ppsi/proto-ext-whiterabbit/wr-constants.h\n                          ppsi/include/ppsi/ieee1588_types.h'
+          range: 7-0
+          x-wbgen:
+            access_bus: READ_ONLY
+            access_dev: WRITE_ONLY
+            type: SLV
+  - reg:
+      name: WDIAG_ASTAT
+      description: 'WRPC Diag: AUX state'
+      width: 32
+      access: ro
+      address: 0x14
+      children:
+      - field:
+          name: aux
+          description: AUX channel
+          comment: 'A vector of bits, one bit per channel\n                     0: not valid\n                     1:valid'
+          range: 7-0
+          x-wbgen:
+            access_bus: READ_ONLY
+            access_dev: WRITE_ONLY
+            type: SLV
+  - reg:
+      name: WDIAG_TXFCNT
+      description: 'WRPC Diag: Tx PTP Frame cnts'
+      comment: Number of transmitted PTP Frames
+      width: 32
+      access: ro
+      address: 0x18
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_RXFCNT
+      description: 'WRPC Diag: Rx PTP Frame cnts'
+      comment: Number of received PTP Frames
+      width: 32
+      access: ro
+      address: 0x1c
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_SEC_MSB
+      description: 'WRPC Diag:local time [msb of s]'
+      comment: Local Time expressed in seconds since epoch (TAI)
+      width: 32
+      access: ro
+      address: 0x20
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_SEC_LSB
+      description: 'WRPC Diag: local time [lsb of s]'
+      comment: Local Time expressed in seconds since epoch (TAI)
+      width: 32
+      access: ro
+      address: 0x24
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_NS
+      description: 'WRPC Diag: local time [ns]'
+      comment: Nanoseconds part of the Local Time expressed in seconds since epoch (TAI)
+      width: 32
+      access: ro
+      address: 0x28
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_MU_MSB
+      description: 'WRPC Diag: Round trip (mu) [msb of ps]'
+      width: 32
+      access: ro
+      address: 0x2c
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_MU_LSB
+      description: 'WRPC Diag: Round trip (mu) [lsb of ps]'
+      width: 32
+      access: ro
+      address: 0x30
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_DMS_MSB
+      description: 'WRPC Diag: Master-slave delay (dms) [msb of ps]'
+      width: 32
+      access: ro
+      address: 0x34
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_DMS_LSB
+      description: 'WRPC Diag: Master-slave delay (dms) [lsb of ps]'
+      width: 32
+      access: ro
+      address: 0x38
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_ASYM
+      description: 'WRPC Diag: Total link asymmetry [ps]'
+      width: 32
+      access: ro
+      address: 0x3c
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_CKO
+      description: 'WRPC Diag: Clock offset (cko) [ps]'
+      width: 32
+      access: ro
+      address: 0x40
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_SETP
+      description: 'WRPC Diag: Phase setpoint (setp) [ps]'
+      width: 32
+      access: ro
+      address: 0x44
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_UCNT
+      description: 'WRPC Diag: Update counter (ucnt)'
+      width: 32
+      access: ro
+      address: 0x48
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
+  - reg:
+      name: WDIAG_TEMP
+      description: 'WRPC Diag: Board temperature [C degree]'
+      width: 32
+      access: ro
+      address: 0x4c
+      x-wbgen:
+        access_bus: READ_ONLY
+        access_dev: WRITE_ONLY
+        field_description: Data
+        type: SLV
--- a/modules/wrc_core/wrc_diags_wb.vhd
+++ b/modules/wrc_core/wrc_diags_wb.vhd
--- a/modules/wrc_core/wrc_diags_wb.wb
+++ b/modules/wrc_core/wrc_diags_wb.wb
-- -*- Mode: LUA; tab-width: 2 -*-
-
-peripheral {
-   name = "WR Core Diagnostics";
-   description = "Diagnostics information accessible via WR";
-   prefix = "wrc_diags";
-   hdl_entity = "wrc_diags_wb";
-   version = 1;
-
-  reg {
-    name = "Ctrl";
-    prefix = "CTRL";
-    field {
-      name        = "WR DIAG data valid";
-      prefix      = "DATA_VALID";
-      description = "0: valid\
-                     1:transcient";
-      type        = BIT;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-    field {
-      name        = "WR DIAG data snapshot";
-      prefix      = "DATA_SNAPSHOT";
-      description = "1: snapshot data (data in registers will not change aveter VALID becomes true)";
-      type        = BIT;
-      access_bus  = WRITE_READ;
-      access_dev  = READ_ONLY;
-      align       = 8;
-    };
-  };
-  reg {
-    name = "WRPC Diag: servo status";
-    prefix = "WDIAG_SSTAT";
-    field {
-      name        = "WR valid";
-      prefix      = "wr_mode";
-      description = "0: not valid\
-                     1:valid";
-      type        = BIT;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-    field {
-      name        = "Servo State";
-      prefix      = "servostate";
-      description = "0: Uninitialized\
-                     1: SYNC_NSEC\
-                     2: SYNC_TAI\
-                     3: SYNC_PHASE\
-                     4: TRACK_PHASE\
-                     5: WAIT_OFFSET_STABLE";
-      type        = SLV;
-      size        = 4;
-      align       = 8;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Port status";
-    prefix = "WDIAG_PSTAT";
-    field {
-      name        = "Link Status";
-      prefix      = "link";
-      description = "0: link down\
-                     1: link up";
-      type        = BIT;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-    field {
-      name        = "PLL Locked";
-      prefix      = "locked";
-      description = "0: not locked\
-                     1: locked";
-      type        = BIT;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: PTP state";
-    prefix = "WDIAG_PTPSTAT";
-
-    field {
-      name        = "PTP State";
-      prefix      = "ptpstate";
-      description = "0: NONE\
-                     1: PPS_INITIALIZING\
-                     2: PPS_FAULTY\
-                     3: disabled\
-                     4: PPS_LISTENING\
-                     5: PPS_PRE_MASTER\
-                     6: PPS_MASTER\
-                     7: PPS_PASSIVE\
-                     8: PPS_UNCALIBRATED\
-                     9: PPS_SLAVE\
-                     100-116: WR STATES\
-                     see: ppsi/proto-ext-whiterabbit/wr-constants.h\
-                          ppsi/include/ppsi/ieee1588_types.h";
-      type        = SLV;
-      size        = 8;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: AUX state";
-    prefix = "WDIAG_ASTAT";
-
-    field {
-      name        = "AUX channel";
-      prefix      = "aux";
-      description = "A vector of bits, one bit per channel\
-                     0: not valid\
-                     1:valid";
-      type        = SLV;
-      size        = 8;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Tx PTP Frame cnts";
-    prefix = "WDIAG_TXFCNT";
-    description = "Number of transmitted PTP Frames";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Rx PTP Frame cnts";
-    description = "Number of received PTP Frames";
-    prefix = "WDIAG_RXFCNT";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag:local time [msb of s]";
-    prefix = "WDIAG_SEC_MSB";
-    description = "Local Time expressed in seconds since epoch (TAI)";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: local time [lsb of s]";
-    description = "Local Time expressed in seconds since epoch (TAI)";
-    prefix = "WDIAG_SEC_LSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: local time [ns]";
-    description = "Nanoseconds part of the Local Time expressed in seconds since epoch (TAI)";
-    prefix = "WDIAG_NS";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Round trip (mu) [msb of ps]";
-    prefix = "WDIAG_MU_MSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Round trip (mu) [lsb of ps]";
-    prefix = "WDIAG_MU_LSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Master-slave delay (dms) [msb of ps]";
-    prefix = "WDIAG_DMS_MSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Master-slave delay (dms) [lsb of ps]";
-    prefix = "WDIAG_DMS_LSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Total link asymmetry [ps]";
-    prefix = "WDIAG_ASYM";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Clock offset (cko) [ps]";
-    prefix = "WDIAG_CKO";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Phase setpoint (setp) [ps]";
-    prefix = "WDIAG_SETP";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Update counter (ucnt)";
-    prefix = "WDIAG_UCNT";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Board temperature [C degree]";
-    prefix = "WDIAG_TEMP";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-    };
-  };
-};
--- a/modules/wrc_core/wrc_periph.vhd
+++ b/modules/wrc_core/wrc_periph.vhd
@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-04-04
-- Last update: 2021-01-15
+-- Last update: 2022-01-25
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -43,7 +43,6 @@ library work;
 use work.wrcore_pkg.all;
 use work.wishbone_pkg.all;
 use work.sysc_wbgen2_pkg.all;
-use work.wrc_diags_wbgen2_pkg.all;

 entity wrc_periph is
  generic(
@@ -62,7 +61,8 @@ entity wrc_periph is
    g_diag_id         : integer := 0;
    g_diag_ver        : integer := 0;
    g_diag_ro_size    : integer := 0;
-    g_diag_rw_size    : integer := 0
+    g_diag_rw_size    : integer := 0;
+    g_wdiags_num_words : integer := 64
    );
  port(
    clk_sys_i : in std_logic;
@@ -90,8 +90,8 @@ entity wrc_periph is
    spi_mosi_o  : out std_logic;
    spi_miso_i  : in  std_logic;

-    slave_i : in  t_wishbone_slave_in_array(0 to 3);
-    slave_o : out t_wishbone_slave_out_array(0 to 3);
+    slave_i : in  t_wishbone_slave_in_array(0 to 4);
+    slave_o : out t_wishbone_slave_out_array(0 to 4);

    uart_rxd_i : in  std_logic;
    uart_txd_o : out std_logic;
@@ -141,21 +141,37 @@ architecture struct of wrc_periph is
  signal diag_dat : std_logic_vector(31 downto 0);
  signal diag_out_regs : t_generic_word_array(g_diag_rw_size - 1 downto 0);
  signal diag_in       : t_generic_word_array(g_diag_ro_size + g_diag_rw_size-1 downto 0);
-  signal wrpc_diag_regs_in     : t_wrc_diags_in_registers;
-  signal wrpc_diag_regs_out    : t_wrc_diags_out_registers;

+  signal rst_net_n, rst_net_n_d0 : std_logic;
+  signal rst_wrc_n, rst_wrc_n_d0 : std_logic;
+  
+  
 begin

-  rst_wrc_n_o <= rst_n_i and rst_wrc_n_o_reg;
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        rst_wrc_n_o <= '0';
+      else
+        rst_net_n_o <= rst_net_n_d0;
+        rst_net_n_d0 <= rst_net_n;
+
+        rst_wrc_n_o <= rst_wrc_n_d0;
+        rst_wrc_n_d0 <= rst_wrc_n;
+      end if;
+    end if;
+  end process;
+
  process(clk_sys_i)
  begin
    if rising_edge(clk_sys_i) then
      if(rst_n_i = '0') then
-        rst_net_n_o <= '0';
+        rst_net_n <= '0';
        if g_has_preinitialized_firmware then
-          rst_wrc_n_o_reg <= '1';
+          rst_wrc_n <= '1';
        else
-          rst_wrc_n_o_reg <= '0'; -- no firmware in DPRAM? keep in reset so
+          rst_wrc_n <= '0'; -- no firmware in DPRAM? keep in reset so
                                  -- that the CPU doesn't walk through the
                                  -- whole address space trying to fetch
                                  -- instructions (and sometimes freezing the interconnect)
@@ -163,10 +179,10 @@ begin
      else

        if(sysc_regs_o.rstr_trig_wr_o = '1' and sysc_regs_o.rstr_trig_o = x"deadbee") then
-          rst_wrc_n_o_reg <= not sysc_regs_o.rstr_rst_o;
+          rst_wrc_n <= not sysc_regs_o.rstr_rst_o;
        end if; 
            
-        rst_net_n_o <= not sysc_regs_o.gpsr_net_rst_o;
+        rst_net_n <= not sysc_regs_o.gpsr_net_rst_o;
      end if; 
    end if; 
  end process;
@@ -411,7 +427,7 @@ begin
    port map (
      rst_n_i    => rst_n_i,
      clk_sys_i  => clk_sys_i,
-      wb_adr_i   => slave_i(0).adr(6 downto 2), -- shift address for word addressing
+      wb_adr_i   => slave_i(0).adr(5 downto 2), -- shift address for word addressing
      wb_dat_i   => slave_i(0).dat,
      wb_dat_o   => slave_o(0).dat,
      wb_cyc_i   => slave_i(0).cyc,
@@ -483,51 +499,20 @@ begin
  --------------------------------------

  -- access through WB (PCI/VME/application) to diagnostics of WRPC
-  DIAGS: xwr_diags_wb
+  DIAGS: entity work.wrc_diags_dpram
    generic map(
-      g_interface_mode      => PIPELINED,
-      g_address_granularity => BYTE
+      g_size => g_wdiags_num_words
    )
    port map(
      rst_n_i   => rst_n_i,
      clk_sys_i => clk_sys_i,

-      slave_i   => slave_i(3),
-      slave_o   => slave_o(3),
+      slave_user_i   => slave_i(3),
+      slave_user_o   => slave_o(3),

-      regs_i    => wrpc_diag_regs_in,
-      regs_o    => wrpc_diag_regs_out
+      slave_wrc_i    => SLAVE_I(4),
+      slave_wrc_o    => SLAVE_O(4)
    );

-   -- the information written to syscon WB registers by LM32 are available to the
-   -- user via diag WB registers
-   -- It might look strange that we use two WB modules for that. Since both LM32
-   -- and user application need to access these registers through the same
-   -- wishbone interface we would needed these registers to be R/W. By creating
-   -- another module (xwr_diags_wb) we make read-only registers to be read by
-   -- the external tool. We want to minimize the possibility of user application
-   -- overwriting these values, thus we want them to be read-only.
-   sysc_regs_i.wdiag_ctrl_data_snapshot_i      <= wrpc_diag_regs_out.ctrl_data_snapshot_o;
-   wrpc_diag_regs_in.ctrl_data_valid_i         <= sysc_regs_o.wdiag_ctrl_data_valid_o;
-   wrpc_diag_regs_in.wdiag_sstat_wr_mode_i     <= sysc_regs_o.wdiag_sstat_wr_mode_o;
-   wrpc_diag_regs_in.wdiag_sstat_servostate_i  <= sysc_regs_o.wdiag_sstat_servostate_o;
-   wrpc_diag_regs_in.wdiag_pstat_link_i        <= sysc_regs_o.wdiag_pstat_link_o;
-   wrpc_diag_regs_in.wdiag_pstat_locked_i      <= sysc_regs_o.wdiag_pstat_locked_o;
-   wrpc_diag_regs_in.wdiag_ptpstat_ptpstate_i  <= sysc_regs_o.wdiag_ptpstat_ptpstate_o;
-   wrpc_diag_regs_in.wdiag_astat_aux_i         <= sysc_regs_o.wdiag_astat_aux_o;
-   wrpc_diag_regs_in.wdiag_txfcnt_i            <= sysc_regs_o.wdiag_txfcnt_o;
-   wrpc_diag_regs_in.wdiag_rxfcnt_i            <= sysc_regs_o.wdiag_rxfcnt_o;
-   wrpc_diag_regs_in.wdiag_sec_msb_i           <= sysc_regs_o.wdiag_sec_msb_o;
-   wrpc_diag_regs_in.wdiag_sec_lsb_i           <= sysc_regs_o.wdiag_sec_lsb_o;
-   wrpc_diag_regs_in.wdiag_ns_i                <= sysc_regs_o.wdiag_ns_o;
-   wrpc_diag_regs_in.wdiag_mu_msb_i            <= sysc_regs_o.wdiag_mu_msb_o;
-   wrpc_diag_regs_in.wdiag_mu_lsb_i            <= sysc_regs_o.wdiag_mu_lsb_o;
-   wrpc_diag_regs_in.wdiag_dms_msb_i           <= sysc_regs_o.wdiag_dms_msb_o;
-   wrpc_diag_regs_in.wdiag_dms_lsb_i           <= sysc_regs_o.wdiag_dms_lsb_o;
-   wrpc_diag_regs_in.wdiag_asym_i              <= sysc_regs_o.wdiag_asym_o;
-   wrpc_diag_regs_in.wdiag_cko_i               <= sysc_regs_o.wdiag_cko_o;
-   wrpc_diag_regs_in.wdiag_setp_i              <= sysc_regs_o.wdiag_setp_o;
-   wrpc_diag_regs_in.wdiag_ucnt_i              <= sysc_regs_o.wdiag_ucnt_o;
-   wrpc_diag_regs_in.wdiag_temp_i              <= sysc_regs_o.wdiag_temp_o;

 end struct;
--- a/modules/wrc_core/wrc_syscon_pkg.vhd
+++ b/modules/wrc_core/wrc_syscon_pkg.vhd
--- a/modules/wrc_core/wrc_syscon_regs.h
+++ b/modules/wrc_core/wrc_syscon_regs.h
@@ -3,7 +3,7 @@

  * File           : wrc_syscon_regs.h
  * Author         : auto-generated by wbgen2 from wrc_syscon_wb.wb
-  * Created        : Mon Nov 27 13:37:56 2017
+  * Created        : Sat Jun 19 00:30:19 2021
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
@@ -208,77 +208,6 @@
 #define SYSC_DIAG_CR_RW                       WBGEN2_GEN_MASK(31, 1)

 /* definitions for register: User Diag: data to read/write */
-
-/* definitions for register: WRPC Diag: ctrl */
-
-/* definitions for field: WR DIAG data valid in reg: WRPC Diag: ctrl */
-#define SYSC_WDIAG_CTRL_DATA_VALID            WBGEN2_GEN_MASK(0, 1)
-
-/* definitions for field: WR DIAG data snapshot in reg: WRPC Diag: ctrl */
-#define SYSC_WDIAG_CTRL_DATA_SNAPSHOT         WBGEN2_GEN_MASK(8, 1)
-
-/* definitions for register: WRPC Diag: servo status */
-
-/* definitions for field: WR valid in reg: WRPC Diag: servo status */
-#define SYSC_WDIAG_SSTAT_WR_MODE              WBGEN2_GEN_MASK(0, 1)
-
-/* definitions for field: Servo State in reg: WRPC Diag: servo status */
-#define SYSC_WDIAG_SSTAT_SERVOSTATE_MASK      WBGEN2_GEN_MASK(8, 4)
-#define SYSC_WDIAG_SSTAT_SERVOSTATE_SHIFT     8
-#define SYSC_WDIAG_SSTAT_SERVOSTATE_W(value)  WBGEN2_GEN_WRITE(value, 8, 4)
-#define SYSC_WDIAG_SSTAT_SERVOSTATE_R(reg)    WBGEN2_GEN_READ(reg, 8, 4)
-
-/* definitions for register: WRPC Diag: Port status */
-
-/* definitions for field: Link Status in reg: WRPC Diag: Port status */
-#define SYSC_WDIAG_PSTAT_LINK                 WBGEN2_GEN_MASK(0, 1)
-
-/* definitions for field: PLL Locked in reg: WRPC Diag: Port status */
-#define SYSC_WDIAG_PSTAT_LOCKED               WBGEN2_GEN_MASK(1, 1)
-
-/* definitions for register: WRPC Diag: PTP state */
-
-/* definitions for field: PTP State in reg: WRPC Diag: PTP state */
-#define SYSC_WDIAG_PTPSTAT_PTPSTATE_MASK      WBGEN2_GEN_MASK(0, 8)
-#define SYSC_WDIAG_PTPSTAT_PTPSTATE_SHIFT     0
-#define SYSC_WDIAG_PTPSTAT_PTPSTATE_W(value)  WBGEN2_GEN_WRITE(value, 0, 8)
-#define SYSC_WDIAG_PTPSTAT_PTPSTATE_R(reg)    WBGEN2_GEN_READ(reg, 0, 8)
-
-/* definitions for register: WRPC Diag: AUX state */
-
-/* definitions for field: AUX channel in reg: WRPC Diag: AUX state */
-#define SYSC_WDIAG_ASTAT_AUX_MASK             WBGEN2_GEN_MASK(0, 8)
-#define SYSC_WDIAG_ASTAT_AUX_SHIFT            0
-#define SYSC_WDIAG_ASTAT_AUX_W(value)         WBGEN2_GEN_WRITE(value, 0, 8)
-#define SYSC_WDIAG_ASTAT_AUX_R(reg)           WBGEN2_GEN_READ(reg, 0, 8)
-
-/* definitions for register: WRPC Diag: Tx PTP Frame cnts */
-
-/* definitions for register: WRPC Diag: Rx PTP Frame cnts */
-
-/* definitions for register: WRPC Diag:local time [msb of s] */
-
-/* definitions for register: WRPC Diag: local time [lsb of s] */
-
-/* definitions for register: WRPC Diag: local time [ns] */
-
-/* definitions for register: WRPC Diag: Round trip (mu) [msb of ps] */
-
-/* definitions for register: WRPC Diag: Round trip (mu) [lsb of ps] */
-
-/* definitions for register: WRPC Diag: Master-slave delay (dms) [msb of ps] */
-
-/* definitions for register: WRPC Diag: Master-slave delay (dms) [lsb of ps] */
-
-/* definitions for register: WRPC Diag: Total link asymmetry [ps] */
-
-/* definitions for register: WRPC Diag: Clock offset (cko) [ps] */
-
-/* definitions for register: WRPC Diag: Phase setpoint (setp) [ps] */
-
-/* definitions for register: WRPC Diag: Update counter (ucnt) */
-
-/* definitions for register: WRPC Diag: Board temperature [C degree] */
 /* [0x0]: REG Syscon reset register */
 #define SYSC_REG_RSTR 0x00000000
 /* [0x4]: REG GPIO Set/Readback Register */
@@ -303,42 +232,4 @@
 #define SYSC_REG_DIAG_CR 0x00000028
 /* [0x2c]: REG User Diag: data to read/write */
 #define SYSC_REG_DIAG_DAT 0x0000002c
-/* [0x30]: REG WRPC Diag: ctrl */
-#define SYSC_REG_WDIAG_CTRL 0x00000030
-/* [0x34]: REG WRPC Diag: servo status */
-#define SYSC_REG_WDIAG_SSTAT 0x00000034
-/* [0x38]: REG WRPC Diag: Port status */
-#define SYSC_REG_WDIAG_PSTAT 0x00000038
-/* [0x3c]: REG WRPC Diag: PTP state */
-#define SYSC_REG_WDIAG_PTPSTAT 0x0000003c
-/* [0x40]: REG WRPC Diag: AUX state */
-#define SYSC_REG_WDIAG_ASTAT 0x00000040
-/* [0x44]: REG WRPC Diag: Tx PTP Frame cnts */
-#define SYSC_REG_WDIAG_TXFCNT 0x00000044
-/* [0x48]: REG WRPC Diag: Rx PTP Frame cnts */
-#define SYSC_REG_WDIAG_RXFCNT 0x00000048
-/* [0x4c]: REG WRPC Diag:local time [msb of s] */
-#define SYSC_REG_WDIAG_SEC_MSB 0x0000004c
-/* [0x50]: REG WRPC Diag: local time [lsb of s] */
-#define SYSC_REG_WDIAG_SEC_LSB 0x00000050
-/* [0x54]: REG WRPC Diag: local time [ns] */
-#define SYSC_REG_WDIAG_NS 0x00000054
-/* [0x58]: REG WRPC Diag: Round trip (mu) [msb of ps] */
-#define SYSC_REG_WDIAG_MU_MSB 0x00000058
-/* [0x5c]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
-#define SYSC_REG_WDIAG_MU_LSB 0x0000005c
-/* [0x60]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
-#define SYSC_REG_WDIAG_DMS_MSB 0x00000060
-/* [0x64]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
-#define SYSC_REG_WDIAG_DMS_LSB 0x00000064
-/* [0x68]: REG WRPC Diag: Total link asymmetry [ps] */
-#define SYSC_REG_WDIAG_ASYM 0x00000068
-/* [0x6c]: REG WRPC Diag: Clock offset (cko) [ps] */
-#define SYSC_REG_WDIAG_CKO 0x0000006c
-/* [0x70]: REG WRPC Diag: Phase setpoint (setp) [ps] */
-#define SYSC_REG_WDIAG_SETP 0x00000070
-/* [0x74]: REG WRPC Diag: Update counter (ucnt) */
-#define SYSC_REG_WDIAG_UCNT 0x00000074
-/* [0x78]: REG WRPC Diag: Board temperature [C degree] */
-#define SYSC_REG_WDIAG_TEMP 0x00000078
 #endif
--- a/modules/wrc_core/wrc_syscon_wb.vhd
+++ b/modules/wrc_core/wrc_syscon_wb.vhd
--- a/modules/wrc_core/wrc_syscon_wb.wb
+++ b/modules/wrc_core/wrc_syscon_wb.wb
@@ -444,276 +444,4 @@ peripheral {
      load = LOAD_EXT;
    };
  };
-  reg {
-    name = "WRPC Diag: ctrl";
-    prefix = "WDIAG_CTRL";
-    field {
-      name        = "WR DIAG data valid";
-      prefix      = "DATA_VALID";
-      description = "0: valid\
-                     1: transcient";
-      type        = BIT;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-    field {
-      name        = "WR DIAG data snapshot";
-      prefix      = "DATA_SNAPSHOT";
-      description = "1: snapshot data (data in registers will not change aveter VALID becomes true)";
-      type        = BIT;
-      access_bus  = READ_ONLY;
-      access_dev  = WRITE_ONLY;
-      align       = 8;
-    };
-  };
-  reg {
-    name = "WRPC Diag: servo status";
-    prefix = "WDIAG_SSTAT";
-    field {
-      name        = "WR valid";
-      prefix      = "wr_mode";
-      description = "0: not valid\1:valid";
-      type        = BIT;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-    field {
-      name        = "Servo State";
-      prefix      = "servostate";
-      description = "0: Uninitialized\
-                     1: SYNC_NSEC\
-                     2: SYNC_TAI\
-                     3: SYNC_PHASE\
-                     4: TRACK_PHASE\
-                     5: WAIT_OFFSET_STABLE";
-      type        = SLV;
-      size        = 4;
-      align       = 8;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Port status";
-    prefix = "WDIAG_PSTAT";
-    field {
-      name        = "Link Status";
-      prefix      = "link";
-      description = "0: link down\
-                     1: link up";
-      type        = BIT;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-    field {
-      name        = "PLL Locked";
-      prefix      = "locked";
-      description = "0: not locked\
-                     1: locked";
-      type        = BIT;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: PTP state";
-    prefix = "WDIAG_PTPSTAT";
-
-    field {
-      name        = "PTP State";
-      prefix      = "ptpstate";
-      description = "0: NONE\
-                     1: PPS_INITIALIZING\
-                     2: PPS_FAULTY\
-                     3: disabled\
-                     4: PPS_LISTENING\
-                     5: PPS_PRE_MASTER\
-                     6: PPS_MASTER\
-                     7: PPS_PASSIVE\
-                     8: PPS_UNCALIBRATED\
-                     9: PPS_SLAVE\
-                     100-116: WR STATES\
-                     see: ppsi/proto-ext-whiterabbit/wr-constants.h\
-                          ppsi/include/ppsi/ieee1588_types.h";
-      type        = SLV;
-      size        = 8;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: AUX state";
-    prefix = "WDIAG_ASTAT";
-
-    field {
-      name        = "AUX channel";
-      prefix      = "aux";
-      description = "A vector of bits, one bit per channel\
-                     0: not valid\
-                     1:valid";
-      type        = SLV;
-      size        = 8;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Tx PTP Frame cnts";
-    prefix = "WDIAG_TXFCNT";
-    description = "Number of transmitted PTP Frames";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Rx PTP Frame cnts";
-    description = "Number of received PTP Frames";
-    prefix = "WDIAG_RXFCNT";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag:local time [msb of s]";
-    prefix = "WDIAG_SEC_MSB";
-    description = "Local Time expressed in seconds since epoch (TAI)";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: local time [lsb of s]";
-    description = "Local Time expressed in seconds since epoch (TAI)";
-    prefix = "WDIAG_SEC_LSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: local time [ns]";
-    description = "Nanoseconds part of the Local Time expressed in seconds since epoch (TAI)";
-    prefix = "WDIAG_NS";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Round trip (mu) [msb of ps]";
-    prefix = "WDIAG_MU_MSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Round trip (mu) [lsb of ps]";
-    prefix = "WDIAG_MU_LSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Master-slave delay (dms) [msb of ps]";
-    prefix = "WDIAG_DMS_MSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Master-slave delay (dms) [lsb of ps]";
-    prefix = "WDIAG_DMS_LSB";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Total link asymmetry [ps]";
-    prefix = "WDIAG_ASYM";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Clock offset (cko) [ps]";
-    prefix = "WDIAG_CKO";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Phase setpoint (setp) [ps]";
-    prefix = "WDIAG_SETP";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Update counter (ucnt)";
-    prefix = "WDIAG_UCNT";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
-  reg {
-    name = "WRPC Diag: Board temperature [C degree]";
-    prefix = "WDIAG_TEMP";
-    field {
-      name = "Data";
-      size = 32;
-      type = SLV;
-      access_bus  = READ_WRITE;
-      access_dev  = READ_ONLY;
-    };
-  };
 };
--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-05-11
-- Last update: 2021-01-15
+-- Last update: 2022-01-17
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -38,7 +38,6 @@ library work;
 use work.genram_pkg.all;
 use work.wishbone_pkg.all;
 use work.sysc_wbgen2_pkg.all;
-use work.wrc_diags_wbgen2_pkg.all;
 use work.wr_fabric_pkg.all;
 use work.endpoint_pkg.all;
 use work.softpll_pkg.all;
@@ -142,22 +141,6 @@ package wrcore_pkg is
  -----------------------------------------------------------------------------
  -- PERIPHERIALS
  -----------------------------------------------------------------------------
-  component xwr_diags_wb is
-    generic(
-      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
-      g_address_granularity : t_wishbone_address_granularity := WORD
-    );
-    port (
-      rst_n_i   : in  std_logic;
-      clk_sys_i : in  std_logic;
-
-      slave_i   : in  t_wishbone_slave_in;
-      slave_o   : out t_wishbone_slave_out;
-
-      regs_i    : in  t_wrc_diags_in_registers;
-      regs_o    : out t_wrc_diags_out_registers
-    );
-  end component;

  constant c_wrc_periph0_sdb : t_sdb_device := (
    abi_class     => x"0000",              -- undocumented device
@@ -240,6 +223,22 @@ package wrcore_pkg is
        date      => x"20170424",
        name      => "WR-Periph-WRPC-DIAG")));

+  constant c_wrc_periph5_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"779c544a",
+        version   => x"00000001",
+        date      => x"20210620",
+        name      => "WR-Periph-DIAG-PRIV")));
+
  component wrc_periph is
    generic(
      g_board_name      : string  := "NA  ";
@@ -282,8 +281,8 @@ package wrcore_pkg is
      spi_ncs_o   : out std_logic;
      spi_mosi_o  : out std_logic;
      spi_miso_i  : in  std_logic;
-      slave_i     : in  t_wishbone_slave_in_array(0 to 3);
-      slave_o     : out t_wishbone_slave_out_array(0 to 3);
+      slave_i     : in  t_wishbone_slave_in_array(0 to 4);
+      slave_o     : out t_wishbone_slave_out_array(0 to 4);
      uart_rxd_i  : in  std_logic;
      uart_txd_o  : out std_logic;
      owr_pwren_o : out std_logic_vector(1 downto 0);
@@ -384,6 +383,7 @@ package wrcore_pkg is
      g_tx_runt_padding           : boolean                        := true;
      g_dpram_initf               : string                         := "default";
      g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+      g_use_platform_specific_dpram : boolean                      := false;
      g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
      g_address_granularity       : t_wishbone_address_granularity := BYTE;
      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
@@ -538,6 +538,7 @@ package wrcore_pkg is
      g_tx_runt_padding           : boolean                        := true;
      g_dpram_initf               : string                         := "default";
      g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+      g_use_platform_specific_dpram : boolean                      := false;
      g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
      g_address_granularity       : t_wishbone_address_granularity := BYTE;
      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
@@ -785,6 +786,20 @@ package wrcore_pkg is
      dac_din_o   : out std_logic);
  end component;

+  component wrc_platform_dpram is
+    generic (
+      g_size                  : natural;
+      g_init_file             : string;
+      g_must_have_init_file   : boolean);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave1_i  : in  t_wishbone_slave_in;
+      slave1_o  : out t_wishbone_slave_out;
+      slave2_i  : in  t_wishbone_slave_in;
+      slave2_o  : out t_wishbone_slave_out);
+  end component wrc_platform_dpram;
+  
 end wrcore_pkg;

 package body wrcore_pkg is

--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-02
-- Last update: 2020-11-02
+-- Last update: 2022-01-17
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -92,6 +92,7 @@ entity xwr_core is
    g_tx_runt_padding           : boolean                        := true;
    g_dpram_initf               : string                         := "";
    g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+    g_use_platform_specific_dpram        : boolean := FALSE;
    g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
    g_address_granularity       : t_wishbone_address_granularity := BYTE;
    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
@@ -103,7 +104,8 @@ entity xwr_core is
    g_diag_id                   : integer                        := 0;
    g_diag_ver                  : integer                        := 0;
    g_diag_ro_size              : integer                        := 0;
-    g_diag_rw_size              : integer                        := 0);
+    g_diag_rw_size              : integer                        := 0
+    );
  port(
    ---------------------------------------------------------------------------
    -- Clocks/resets
@@ -314,7 +316,8 @@ begin
      g_diag_id                   => g_diag_id,
      g_diag_ver                  => g_diag_ver,
      g_diag_ro_size              => g_diag_ro_size,
-      g_diag_rw_size              => g_diag_rw_size
+      g_diag_rw_size              => g_diag_rw_size,
+      g_use_platform_specific_dpram => g_use_platform_specific_dpram
      )
    port map(
      clk_sys_i     => clk_sys_i,

--- a/modules/wrc_core/xwrc_diags_wb.vhd
+++ b/modules/wrc_core/xwrc_diags_wb.vhd
-------------------------------------------------------------------------------
-- Title      : WR PTP Core Diagnostics
-- Project    : WhiteRabbit
-------------------------------------------------------------------------------
-- File       : xwrc_diags_wb.vhd
-- Author     : Maciej Lipinski <maciej.lipinski@cern.ch>
-- Company    : CERN
-- Created    : 2017-04-24
-- Platform   : FPGA-generics
-- Standard   : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Wrapper for wrc_diags_wb. Uses types instead of std_logic signals and
-- can use pipelined or classic wishbone.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE.  See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use work.wishbone_pkg.all;
-use work.wrc_diags_wbgen2_pkg.all;
-
-entity xwr_diags_wb is
-  generic(
-    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
-    g_address_granularity : t_wishbone_address_granularity := WORD
-  );
-  port (
-    rst_n_i   : in  std_logic;
-    clk_sys_i : in  std_logic;
-
-    slave_i   : in  t_wishbone_slave_in;
-    slave_o   : out t_wishbone_slave_out;
-
-    regs_i    : in  t_wrc_diags_in_registers;
-    regs_o    : out t_wrc_diags_out_registers
-  );
-end xwr_diags_wb;
-
-architecture syn of xwr_diags_wb is
-
-  component wrc_diags_wb is
-    port (
-      rst_n_i                                  : in     std_logic;
-      clk_sys_i                                : in     std_logic;
-      wb_adr_i                                 : in     std_logic_vector(4 downto 0);
-      wb_dat_i                                 : in     std_logic_vector(31 downto 0);
-      wb_dat_o                                 : out    std_logic_vector(31 downto 0);
-      wb_cyc_i                                 : in     std_logic;
-      wb_sel_i                                 : in     std_logic_vector(3 downto 0);
-      wb_stb_i                                 : in     std_logic;
-      wb_we_i                                  : in     std_logic;
-      wb_ack_o                                 : out    std_logic;
-      wb_stall_o                               : out    std_logic;
-      regs_i                                   : in     t_wrc_diags_in_registers;
-      regs_o                                   : out    t_wrc_diags_out_registers
-    );
-  end component;
-
-
-  signal wb_out : t_wishbone_slave_out;
-  signal wb_in  : t_wishbone_slave_in;
-
-begin
-
-  U_Adapter : wb_slave_adapter
-    generic map(
-      g_master_use_struct  => true,
-      g_master_mode        => CLASSIC,
-      g_master_granularity => WORD,
-      g_slave_use_struct   => false,
-      g_slave_mode         => g_interface_mode,
-      g_slave_granularity  => g_address_granularity)
-    port map (
-      clk_sys_i  => clk_sys_i,
-      rst_n_i    => rst_n_i,
-      master_i   => wb_out,
-      master_o   => wb_in,
-      sl_adr_i   => slave_i.adr,
-      sl_dat_i   => slave_i.dat,
-      sl_sel_i   => slave_i.sel,
-      sl_cyc_i   => slave_i.cyc,
-      sl_stb_i   => slave_i.stb,
-      sl_we_i    => slave_i.we,
-      sl_dat_o   => slave_o.dat, 
-      sl_ack_o   => slave_o.ack,
-      sl_stall_o => slave_o.stall);
-
-  WRAPPED_DIAGS: wrc_diags_wb
-    port map(
-      rst_n_i    => rst_n_i,
-      clk_sys_i  => clk_sys_i,
-      wb_adr_i   => wb_in.adr(4 downto 0),
-      wb_dat_i   => wb_in.dat,
-      wb_dat_o   => wb_out.dat,
-      wb_cyc_i   => wb_in.cyc,
-      wb_sel_i   => wb_in.sel,
-      wb_stb_i   => wb_in.stb,
-      wb_we_i    => wb_in.we,
-      wb_ack_o   => wb_out.ack,
-      wb_stall_o => wb_out.stall,
-      regs_i     => regs_i,
-      regs_o     => regs_o);
-
-  slave_o.err <= '0';
-  slave_o.rty <= '0';
-
-end syn;
-
-
-
--- a/platform/xilinx/Manifest.py
+++ b/platform/xilinx/Manifest.py
 if (syn_device[0:4].upper()=="XC7A" or syn_device[0:4].upper()=="XC7K" or
        syn_device[0:4].upper()=="XCZU"):
-	files = [ "wr_xilinx_pkg.vhd", "xwrc_platform_vivado.vhd" ]
+	files = [ "wr_xilinx_pkg.vhd", "xwrc_platform_vivado.vhd", "wrc_dpram/wrc_platform_dpram_ultrascale.vhd" ]
 else:
 	files = [ "wr_xilinx_pkg.vhd", "xwrc_platform_xilinx.vhd" ]
 modules = {"local" : ["wr_gtp_phy", "chipscope"]}
+
+#if (syn_device[0:4].upper()=="XCKU" or syn_device[0:4].upper()=="XC7U" ):
+#	files += [ "wrc_dpram/wrc_platform_dpram_ultrascale.vhd" ]
--- a/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd
@@ -219,21 +219,21 @@ architecture rtl of wr_gthe4_phy_family7_xilinx_ip is
  end component gtp_bitslide;

  signal rx_clk, tx_clk                                           : std_logic;
-  signal serdes_ready, rx_comma_det, rx_byte_is_aligned, rx_slide : std_logic;
+  signal serdes_ready_a, serdes_ready_txclk, serdes_ready_rxclk, rx_comma_det, rx_byte_is_aligned, rx_slide : std_logic;
  signal rx_synced, rst_rxclk                                     : std_logic;

-  attribute mark_debug : string;
-  attribute mark_debug of serdes_ready : signal is "true";
-  attribute mark_debug of rx_comma_det : signal is "true";
-  attribute mark_debug of rx_byte_is_aligned : signal is "true";
-  attribute mark_debug of rx_slide : signal is "true";
-  attribute mark_debug of rx_synced : signal is "true";
+  -- attribute mark_debug : string;
+  -- attribute mark_debug of serdes_ready : signal is "true";
+  -- attribute mark_debug of rx_comma_det : signal is "true";
+  -- attribute mark_debug of rx_byte_is_aligned : signal is "true";
+  -- attribute mark_debug of rx_slide : signal is "true";
+  -- attribute mark_debug of rx_synced : signal is "true";
  

-  attribute mark_debug of gtwiz_reset_all_in : signal is "true";
-  attribute mark_debug of gtwiz_reset_rx_done_out : signal is "true";
-  attribute mark_debug of gtwiz_buffbypass_rx_done_out : signal is "true";
-  attribute mark_debug of gtwiz_buffbypass_tx_done_out : signal is "true";
+  -- attribute mark_debug of gtwiz_reset_all_in : signal is "true";
+  -- attribute mark_debug of gtwiz_reset_rx_done_out : signal is "true";
+  -- attribute mark_debug of gtwiz_buffbypass_rx_done_out : signal is "true";
+  -- attribute mark_debug of gtwiz_buffbypass_tx_done_out : signal is "true";

  
  signal rx_data_int : std_logic_vector(15 downto 0);
@@ -275,7 +275,7 @@ begin
  
  U_Sync2 : gc_sync_ffs
    port map (
-      clk_i    => tx_clk,
+      clk_i    => rx_clk,
      rst_n_i  => rst_n,
      data_i   => gtwiz_buffbypass_rx_reset_pre,
      synced_o => gtwiz_buffbypass_rx_reset_in);
@@ -299,7 +299,7 @@ begin
      gtp_rx_clk_i             => rx_clk,
      gtp_rx_comma_det_i       => rx_comma_det,
      gtp_rx_byte_is_aligned_i => rx_byte_is_aligned,
-      serdes_ready_i           => serdes_ready,
+      serdes_ready_i           => serdes_ready_rxclk,
      gtp_rx_slide_o           => rx_slide,
      gtp_rx_cdr_rst_o         => open,
      bitslide_o               => rx_bitslide_o,
@@ -442,10 +442,24 @@ begin
  --     tx_k_i               => tx_is_k_swapped,
  --     ready_o              => serdes_ready);

-  serdes_ready <=
+  serdes_ready_a <=
    not (
      gtwiz_reset_all_in or not gtwiz_reset_rx_done_out or not gtwiz_buffbypass_rx_done_out or not gtwiz_buffbypass_tx_done_out);

+  U_Sync_Serdes_RDY1 : gc_sync_ffs
+    port map (
+      clk_i    => rx_clk,
+      rst_n_i  => '1',
+      data_i   => serdes_ready_a,
+      synced_o => serdes_ready_rxclk);
+
+  U_Sync_Serdes_RDY2 : gc_sync_ffs
+    port map (
+      clk_i    => tx_clk,
+      rst_n_i  => '1',
+      data_i   => serdes_ready_a,
+      synced_o => serdes_ready_txclk);
+  
  txctrl0_int <= x"0000";
  txctrl1_int <= x"0000";
  txctrl2_int <= "000000" & tx_is_k_swapped;
@@ -459,7 +473,7 @@ begin
      rx_k_o       <= (others => '0');
      rx_enc_err_o <= '0';
    elsif rising_edge(rx_clk) then
-      if(serdes_ready = '1' and rx_synced = '1') then
+      if(serdes_ready_rxclk = '1' and rx_synced = '1') then
        rx_data_o    <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
        rx_k_o       <= rx_k_int(0) & rx_k_int(1);
        rx_enc_err_o <= '0';  --rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
@@ -474,7 +488,7 @@ begin
  p_gen_tx_disparity : process(tx_clk)
  begin
    if rising_edge(tx_clk) then
-      if serdes_ready = '0' then
+      if serdes_ready_txclk = '0' then
        cur_disp <= RD_MINUS;
      else
        cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
@@ -487,7 +501,7 @@ begin
  tx_out_clk_o <= tx_clk;
  rx_rbclk_o   <= rx_clk;

-  rdy_o        <= serdes_ready and rx_synced;
+  rdy_o        <= serdes_ready_rxclk and rx_synced;
  tx_locked_o  <= '1';
  tx_enc_err_o <= '0';


--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_ooc.xdc
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_ooc.xdc
@@ -54,13 +54,13 @@
 # OOC Synthesis and Hierarchical Designs.

 # Free-running clock constraint
-create_clock -period 16.0 [get_ports gtwiz_reset_clk_freerun_in]
+#create_clock -period 16.0 [get_ports gtwiz_reset_clk_freerun_in]

 # CPLL reference clock constraint (will be overridden by required constraint on IBUFDS_GTE4 input in context)
-create_clock -period 8.0 [get_ports gtrefclk0_in[0]]
+#create_clock -period 8.0 [get_ports gtrefclk0_in[0]]

 # DRP clock constraint for CHANNEL primitive
-create_clock -period 16.0 [get_ports drpclk_in[0]]
+#create_clock -period 16.0 [get_ports drpclk_in[0]]


 ##set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}] -quiet

--- a/platform/xilinx/wrc_dpram/wrc_platform_dpram_ultrascale.vhd
+++ b/platform/xilinx/wrc_dpram/wrc_platform_dpram_ultrascale.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+use work.genram_pkg.all;
+use work.wrcore_pkg.all;
+
+library xpm;
+use xpm.vcomponents.all;
+
+entity wrc_platform_dpram is
+
+  generic (
+    g_size                  : natural := 16384;
+    g_init_file             : string  := "";
+    g_must_have_init_file   : boolean := true);
+
+  port (
+    clk_sys_i : in  std_logic;
+    rst_n_i   : in  std_logic;
+    slave1_i  : in  t_wishbone_slave_in;
+    slave1_o  : out t_wishbone_slave_out;
+
+-- warning: port slave2 is unimplemented as it's not used by the WRCore
+    slave2_i  : in  t_wishbone_slave_in;
+    slave2_o  : out t_wishbone_slave_out);
+
+end entity wrc_platform_dpram;
+
+architecture wrapper of wrc_platform_dpram is
+  constant c_ADDR_WIDTH : integer := f_log2_size(g_size);
+
+  signal dina, douta, doutb : std_logic_vector(31 downto 0);
+  signal ena, enb : std_logic;
+  signal bwea : std_logic_vector(3 downto 0);
+  signal addra, addrb : std_logic_vector(c_ADDR_WIDTH-1 downto 0);
+
+  signal slave1_out : t_wishbone_slave_out;
+  signal slave1_in : t_wishbone_slave_in;
+  
+begin
+
+  slave1_in <= slave1_i;
+
+
+  
+  inst_wrapped_dpram : xpm_memory_sdpram
+    generic map (
+      ADDR_WIDTH_A            => c_ADDR_WIDTH,
+      ADDR_WIDTH_B            => c_ADDR_WIDTH,
+      AUTO_SLEEP_TIME         => 0,
+      BYTE_WRITE_WIDTH_A      => 8,            
+      CLOCKING_MODE           => "common_clock",
+      ECC_MODE                => "no_ecc",
+      MEMORY_INIT_FILE        => "none",
+      MEMORY_INIT_PARAM       => "0", 
+      MEMORY_OPTIMIZATION     => "true",
+      MEMORY_PRIMITIVE        => "ultra",
+      MEMORY_SIZE             => g_size * 32,
+      MESSAGE_CONTROL         => 0,     -- DECIMAL
+      READ_DATA_WIDTH_B       => 32,
+      READ_LATENCY_B          => 1,     -- DECIMAL
+      READ_RESET_VALUE_B      => "0",   -- String
+      USE_EMBEDDED_CONSTRAINT => 0,     -- DECIMAL
+      USE_MEM_INIT            => 0,     -- DECIMAL
+      WAKEUP_TIME             => "disable_sleep",                  -- String
+      WRITE_DATA_WIDTH_A      => 32,
+      WRITE_MODE_B            => "read_first"           
+      )
+    port map (
+      doutb    => doutb,  
+      addra => addra, 
+      addrb => addrb, 
+      clka  => clk_sys_i,
+      clkb => clk_sys_i, 
+      dina => dina, 
+      ena  => '1', 
+      enb => '1',
+      injectdbiterra => '0',  
+      injectsbiterra => '0',  
+      regceb => '1', 
+      rstb => '0',  
+      sleep  => '0',
+      wea => bwea 
+      );
+
+  addra <= slave1_in.adr(f_log2_size(g_size)+1 downto 2);
+  addrb <= slave1_in.adr(f_log2_size(g_size)+1 downto 2);
+  dina <= slave1_in.dat;
+  slave1_out.dat <= doutb;
+  bwea <= slave1_in.sel when (slave1_in.cyc = '1' and slave1_in.stb  = '1' and slave1_in.we = '1') else"0000";
+
+
+  process(clk_sys_i)
+  begin
+    if(rising_edge(clk_sys_i)) then
+      if(rst_n_i = '0') then
+        slave1_out.ack <= '0';
+      else
+        slave1_out.ack <= slave1_in.cyc and slave1_in.stb;
+      end if;
+    end if;
+  end process;
+
+  slave1_out.stall <= '0';
+  slave1_out.err   <= '0';
+  slave1_out.rty   <= '0';
+  
+  slave1_o <= slave1_out;
+  
+end wrapper;
--- a/sim/wrc_syscon_regs.vh
+++ b/sim/wrc_syscon_regs.vh
-`define ADDR_SYSC_RSTR                 7'h0
+`define ADDR_SYSC_RSTR                 6'h0
 `define SYSC_RSTR_TRIG_OFFSET 0
 `define SYSC_RSTR_TRIG 32'h0fffffff
 `define SYSC_RSTR_RST_OFFSET 28
 `define SYSC_RSTR_RST 32'h10000000
-`define ADDR_SYSC_GPSR                 7'h4
+`define ADDR_SYSC_GPSR                 6'h4
 `define SYSC_GPSR_LED_STAT_OFFSET 0
 `define SYSC_GPSR_LED_STAT 32'h00000001
 `define SYSC_GPSR_LED_LINK_OFFSET 1
@@ -32,7 +32,7 @@
 `define SYSC_GPSR_SPI_MOSI 32'h00001000
 `define SYSC_GPSR_SPI_MISO_OFFSET 13
 `define SYSC_GPSR_SPI_MISO 32'h00002000
-`define ADDR_SYSC_GPCR                 7'h8
+`define ADDR_SYSC_GPCR                 6'h8
 `define SYSC_GPCR_LED_STAT_OFFSET 0
 `define SYSC_GPCR_LED_STAT 32'h00000001
 `define SYSC_GPCR_LED_LINK_OFFSET 1
@@ -51,73 +51,38 @@
 `define SYSC_GPCR_SPI_CS 32'h00000800
 `define SYSC_GPCR_SPI_MOSI_OFFSET 12
 `define SYSC_GPCR_SPI_MOSI 32'h00001000
-`define ADDR_SYSC_HWFR                 7'hc
+`define ADDR_SYSC_HWFR                 6'hc
 `define SYSC_HWFR_MEMSIZE_OFFSET 0
 `define SYSC_HWFR_MEMSIZE 32'h0000000f
 `define SYSC_HWFR_STORAGE_TYPE_OFFSET 8
 `define SYSC_HWFR_STORAGE_TYPE 32'h00000300
 `define SYSC_HWFR_STORAGE_SEC_OFFSET 16
 `define SYSC_HWFR_STORAGE_SEC 32'hffff0000
-`define ADDR_SYSC_HWIR                 7'h10
+`define ADDR_SYSC_HWIR                 6'h10
 `define SYSC_HWIR_NAME_OFFSET 0
 `define SYSC_HWIR_NAME 32'hffffffff
-`define ADDR_SYSC_SDBFS                7'h14
+`define ADDR_SYSC_SDBFS                6'h14
 `define SYSC_SDBFS_BADDR_OFFSET 0
 `define SYSC_SDBFS_BADDR 32'hffffffff
-`define ADDR_SYSC_TCR                  7'h18
+`define ADDR_SYSC_TCR                  6'h18
 `define SYSC_TCR_TDIV_OFFSET 0
 `define SYSC_TCR_TDIV 32'h00000fff
 `define SYSC_TCR_ENABLE_OFFSET 31
 `define SYSC_TCR_ENABLE 32'h80000000
-`define ADDR_SYSC_TVR                  7'h1c
-`define ADDR_SYSC_DIAG_INFO            7'h20
+`define ADDR_SYSC_TVR                  6'h1c
+`define ADDR_SYSC_DIAG_INFO            6'h20
 `define SYSC_DIAG_INFO_VER_OFFSET 0
 `define SYSC_DIAG_INFO_VER 32'h0000ffff
 `define SYSC_DIAG_INFO_ID_OFFSET 16
 `define SYSC_DIAG_INFO_ID 32'hffff0000
-`define ADDR_SYSC_DIAG_NW              7'h24
+`define ADDR_SYSC_DIAG_NW              6'h24
 `define SYSC_DIAG_NW_RW_OFFSET 0
 `define SYSC_DIAG_NW_RW 32'h0000ffff
 `define SYSC_DIAG_NW_RO_OFFSET 16
 `define SYSC_DIAG_NW_RO 32'hffff0000
-`define ADDR_SYSC_DIAG_CR              7'h28
+`define ADDR_SYSC_DIAG_CR              6'h28
 `define SYSC_DIAG_CR_ADR_OFFSET 0
 `define SYSC_DIAG_CR_ADR 32'h0000ffff
 `define SYSC_DIAG_CR_RW_OFFSET 31
 `define SYSC_DIAG_CR_RW 32'h80000000
-`define ADDR_SYSC_DIAG_DAT             7'h2c
-`define ADDR_SYSC_WDIAG_CTRL           7'h30
-`define SYSC_WDIAG_CTRL_DATA_VALID_OFFSET 0
-`define SYSC_WDIAG_CTRL_DATA_VALID 32'h00000001
-`define SYSC_WDIAG_CTRL_DATA_SNAPSHOT_OFFSET 8
-`define SYSC_WDIAG_CTRL_DATA_SNAPSHOT 32'h00000100
-`define ADDR_SYSC_WDIAG_SSTAT          7'h34
-`define SYSC_WDIAG_SSTAT_WR_MODE_OFFSET 0
-`define SYSC_WDIAG_SSTAT_WR_MODE 32'h00000001
-`define SYSC_WDIAG_SSTAT_SERVOSTATE_OFFSET 8
-`define SYSC_WDIAG_SSTAT_SERVOSTATE 32'h00000f00
-`define ADDR_SYSC_WDIAG_PSTAT          7'h38
-`define SYSC_WDIAG_PSTAT_LINK_OFFSET 0
-`define SYSC_WDIAG_PSTAT_LINK 32'h00000001
-`define SYSC_WDIAG_PSTAT_LOCKED_OFFSET 1
-`define SYSC_WDIAG_PSTAT_LOCKED 32'h00000002
-`define ADDR_SYSC_WDIAG_PTPSTAT        7'h3c
-`define SYSC_WDIAG_PTPSTAT_PTPSTATE_OFFSET 0
-`define SYSC_WDIAG_PTPSTAT_PTPSTATE 32'h000000ff
-`define ADDR_SYSC_WDIAG_ASTAT          7'h40
-`define SYSC_WDIAG_ASTAT_AUX_OFFSET 0
-`define SYSC_WDIAG_ASTAT_AUX 32'h000000ff
-`define ADDR_SYSC_WDIAG_TXFCNT         7'h44
-`define ADDR_SYSC_WDIAG_RXFCNT         7'h48
-`define ADDR_SYSC_WDIAG_SEC_MSB        7'h4c
-`define ADDR_SYSC_WDIAG_SEC_LSB        7'h50
-`define ADDR_SYSC_WDIAG_NS             7'h54
-`define ADDR_SYSC_WDIAG_MU_MSB         7'h58
-`define ADDR_SYSC_WDIAG_MU_LSB         7'h5c
-`define ADDR_SYSC_WDIAG_DMS_MSB        7'h60
-`define ADDR_SYSC_WDIAG_DMS_LSB        7'h64
-`define ADDR_SYSC_WDIAG_ASYM           7'h68
-`define ADDR_SYSC_WDIAG_CKO            7'h6c
-`define ADDR_SYSC_WDIAG_SETP           7'h70
-`define ADDR_SYSC_WDIAG_UCNT           7'h74
-`define ADDR_SYSC_WDIAG_TEMP           7'h78
+`define ADDR_SYSC_DIAG_DAT             6'h2c