wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address space. Default is 128kB (legacy)

platform/xilinx: split platform for vivado to a separate file not to break ise build with unknown primitives

wr_gthe3_phy_family7: assert rx_enc_err when the link is down to reliably force link down event in the PCS

wr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies, more control over resets