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Commit 5e088128 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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wr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies,… 

wr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies, more control over resets
parent 1f3c0302
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Showing with 68 additions and 30 deletions
platform/xilinx/wr_gtp_phy/kintex7-lp/gtx_comma_detect_lp.vhd
View file @ 5e088128
......@@ -29,7 +29,6 @@ architecture rtl of gtx_comma_detect_kintex7_lp is
constant c_IDLE_LENGTH_UP : integer := 500;
constant c_IDLE_LENGTH_LOSS : integer := 1000;
constant c_COMMA_SHIFT_WE_WANT : std_logic_vector(6 downto 0) := "0110000";
-- fixme
signal rx_data_d0 : std_logic_vector(19 downto 0);
......
platform/xilinx/wr_gtp_phy/kintex7-lp/wr_gtx_phy_kintex7_lp.vhd
View file @ 5e088128
......@@ -6,7 +6,7 @@
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
-- Last update: 2019-06-14
-- Last update: 2019-06-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -66,7 +66,7 @@ entity wr_gtx_phy_kintex7_lp is
qpll_clk_i : in std_logic;
qpll_ref_clk_i : in std_logic;
qpll_locked_i : in std_logic;
qpll_reset_o : out std_logic;
-- DMTD clock for phase measurements (done in the PHY module as we need to
-- multiplex between several GTX clock outputs)
......@@ -127,7 +127,11 @@ entity wr_gtx_phy_kintex7_lp is
debug_i : in std_logic_vector(15 downto 0) := x"0000";
debug_o : out std_logic_vector(15 downto 0);
rx_rbclk_sampled_o : out std_logic
rx_rbclk_sampled_o : out std_logic;
fmon_clk_tx_o : out std_logic;
fmon_clk_tx2_o : out std_logic;
fmon_clk_rx_o : out std_logic
);
end wr_gtx_phy_kintex7_lp;
......@@ -161,7 +165,7 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
out_8b_o : out std_logic_vector(7 downto 0));
end component gc_dec_8b10b;
constant c_rxcdrlock_max : integer := 3;
constant c_rxcdrlock_max : integer := 30;
constant c_reset_cnt_max : integer := 64; -- Reset pulse width 64 * 8 = 512 ns
signal rst_synced : std_logic;
......@@ -169,8 +173,6 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
signal rst_d0 : std_logic;
signal reset_counter : unsigned(9 downto 0);
-- signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
signal rx_rec_clk_bufin : std_logic;
signal rx_rec_clk : std_logic;
signal tx_out_clk_bufin : std_logic;
......@@ -196,6 +198,7 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
signal rx_charisk_wrap : std_logic_vector(1 downto 0);
signal rx_disperr_wrap : std_logic_vector(1 downto 0);
signal rx_data_raw : std_logic_vector(19 downto 0);
signal rx_enc_err_o_int : std_logic;
......@@ -207,7 +210,6 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
signal cur_disp : t_8b10b_disparity;
signal tx_reset_done : std_logic;
signal link_up, link_aligned : std_logic;
signal tx_enable, tx_enable_refclk : std_logic;
......@@ -243,7 +245,26 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
signal run_disparity_q0, run_disparity_q1 : std_logic;
signal run_disparity_reg : std_logic;
signal pll_clkfbout_bufin,tx_out_clk_div2_bufin, pll_clkfbout : std_logic;
signal pll_clkfbout_bufin,tx_out_clk_div2_bufin, pll_clkfbout : std_logic;
signal txusrpll_locked : std_logic;
signal qpll_sw_reset : std_logic;
attribute mark_debug : string;
attribute mark_debug of rx_data_raw : signal is "true";
attribute mark_debug of tx_data_i : signal is "true";
attribute mark_debug of tx_k_i : signal is "true";
attribute mark_debug of rx_k_int : signal is "true";
attribute mark_debug of rx_data_int : signal is "true";
attribute mark_debug of link_up : signal is "true";
attribute mark_debug of link_aligned : signal is "true";
attribute mark_debug of tx_sw_reset : signal is "true";
attribute mark_debug of rx_sw_reset : signal is "true";
attribute mark_debug of tx_enable : signal is "true";
attribute mark_debug of rx_enable: signal is "true";
signal txusrpll_reset : std_logic;
begin -- rtl
......@@ -251,9 +272,11 @@ begin -- rtl
tx_enable <= debug_i(1);
rx_enable <= debug_i(2);
rx_sw_reset <= debug_i(3);
qpll_sw_reset <= debug_i(4);
txusrpll_reset <= debug_i(5); -- not tx_rst_done;
-- Near-end PMA loopback if loopen_i active
gtx_loopback <= "010" when loopen_i = '1' else "000";
gtx_loopback <= "010" when debug_i(6) = '1' else "000";
U_SyncTxEnable : gc_sync_ffs
port map
......@@ -292,6 +315,16 @@ begin -- rtl
synced_o => gtx_rx_reset_a
);
U_SyncQPLLReset : gc_sync_ffs
port map
(
clk_i => clk_dmtd_i,
rst_n_i => '1',
data_i => qpll_sw_reset,
synced_o => qpll_reset_o
);
U_SyncTxReset : gc_sync_ffs
port map
(
......@@ -304,8 +337,8 @@ begin -- rtl
U_Sampler_RX : dmtd_sampler
generic map (
g_divide_input_by_2 => true,
g_reverse => false)
g_divide_input_by_2 => false,
g_reverse => true)
port map (
clk_in_i => rx_rec_clk,
clk_dmtd_i => clk_dmtd_i,
......@@ -313,10 +346,10 @@ begin -- rtl
U_Sampler_TX : dmtd_sampler
generic map (
g_divide_input_by_2 => true,
g_reverse => false)
g_divide_input_by_2 => false,
g_reverse => true)
port map (
clk_in_i => tx_out_clk,
clk_in_i => tx_out_clk_div2,
clk_dmtd_i => clk_dmtd_i,
clk_sampled_o => tx_out_clk_sampled);
......@@ -357,7 +390,6 @@ begin -- rtl
gtx_rst <= rst_synced or std_logic(not reset_counter(reset_counter'left));
debug_o(0) <= qpll_locked_i; -- was tx_reset_done
tx_enc_err_o <= '0';
......@@ -486,6 +518,7 @@ begin -- rtl
);
U_GenTxUsrClk : PLLE2_ADV
generic map (
BANDWIDTH =>"HIGH",
......@@ -505,13 +538,14 @@ begin -- rtl
CLKIN1 => tx_out_clk,
CLKIN2 => '0',
CLKINSEL => '1',
LOCKED => txusrpll_locked,
DADDR => "0000000",
DI => x"0000",
DWE => '0',
PWRDWN => '0',
DCLK => '0',
DEN => '0',
RST => gtx_tx_reset_a);
RST => txusrpll_reset );
U_BUF_TxOutClk : BUFG
port map (
......@@ -533,12 +567,8 @@ begin -- rtl
rxpll_lockdet <= rx_cdr_lock_filtered;
rst_done <= rx_rst_done and tx_rst_done;
rst_done_n <= not rst_done;
-- pll_lockdet <= txpll_lockdet and rxpll_lockdet;
everything_ready <= rst_done and txpll_lockdet and rxpll_lockdet; --pll_lockdet;
everything_ready <= rst_done and txpll_lockdet and rxpll_lockdet;
rdy_o <= everything_ready;
-- 2013 August 19: Peterj
......@@ -604,10 +634,14 @@ begin -- rtl
out_8b_o => rx_data_int(7 downto 0));
rx_disp_err <= (others => '0');
debug_o(0) <= qpll_locked_i;
debug_o(1) <= link_up;
debug_o(2) <= link_aligned;
debug_o(3) <= tx_rst_done;
debug_o(4) <= txusrpll_locked;
debug_o(5) <= rx_rst_done;
debug_o(14 downto 7) <= comma_current_pos;
p_gen_rx_outputs : process(rx_rec_clk, gtx_rst)
......@@ -647,4 +681,9 @@ begin -- rtl
-- rx_enc_err_o <= '0';-- rx_enc_err_o_int;
fmon_clk_tx_o <= tx_out_clk;
fmon_clk_tx2_o <= tx_out_clk_div2;
fmon_clk_rx_o <= rx_rec_clk;
end rtl;
platform/xilinx/wr_gtp_phy/kintex7-lp/wr_gtx_phy_kintex7_lp_qpll.vhd
View file @ 5e088128
......@@ -6,7 +6,7 @@
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
-- Last update: 2019-06-05
-- Last update: 2019-06-14
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -71,10 +71,10 @@ entity wr_gtx_phy_kintex7_lp_qpll is
qpll_clk_o : out std_logic;
qpll_ref_clk_o : out std_logic;
locked_o : out std_logic;
locked_o : out std_logic
debug_i : in std_logic_vector(15 downto 0) := x"0000";
debug_o : out std_logic_vector(15 downto 0)
-- debug_i : in std_logic_vector(15 downto 0) := x"0000";
-- debug_o : out std_logic_vector(15 downto 0)
);
end wr_gtx_phy_kintex7_lp_qpll;
......@@ -135,7 +135,7 @@ signal qpll_reset : std_logic;
begin -- rtl
qpll_reset <= rst_i or debug_i(0);
qpll_reset <= rst_i; -- or debug_i(0);
gtxe2_common_i : GTXE2_COMMON
generic map
......
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