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White Rabbit core collection
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e20b26ab
Commit
e20b26ab
authored
Aug 17, 2020
by
Grzegorz Daniluk
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platform/xilinx: global clk_sys signal declaration so that it's available between generate blocks
parent
1272b672
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xwrc_platform_xilinx.vhd
platform/xilinx/xwrc_platform_xilinx.vhd
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platform/xilinx/xwrc_platform_xilinx.vhd
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e20b26ab
...
...
@@ -180,6 +180,7 @@ architecture rtl of xwrc_platform_xilinx is
signal
pll_arst
:
std_logic
:
=
'0'
;
signal
clk_125m_pllref_buf
:
std_logic
;
signal
clk_sys
:
std_logic
;
begin
-- architecture rtl
...
...
@@ -242,7 +243,6 @@ begin -- architecture rtl
gen_spartan6_default_plls
:
if
(
g_fpga_family
=
"spartan6"
)
generate
signal
clk_20m
:
std_logic
;
signal
clk_sys
:
std_logic
;
signal
clk_sys_out
:
std_logic
;
signal
clk_sys_fb
:
std_logic
;
signal
pll_sys_locked
:
std_logic
;
...
...
@@ -467,7 +467,6 @@ begin -- architecture rtl
gen_virtex5_default_plls
:
if
(
g_fpga_family
=
"virtex5"
)
generate
signal
clk_sys
:
std_logic
;
signal
clk_sys_out
:
std_logic
;
signal
clk_sys_fb
:
std_logic
;
signal
pll_sys_locked
:
std_logic
;
...
...
@@ -558,7 +557,6 @@ begin -- architecture rtl
---------------------------------------------------------------------------
gen_kintex7_artix7_default_plls
:
if
(
g_fpga_family
=
"kintex7"
or
g_fpga_family
=
"artix7"
)
generate
signal
clk_sys
:
std_logic
;
signal
clk_sys_out
:
std_logic
;
signal
clk_sys_fb
:
std_logic
;
signal
pll_sys_locked
:
std_logic
;
...
...
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