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White Rabbit core collection
Commit 5c6e5607 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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kintex7-lp: WIP on oversampled version, not sure if it will be needed with the QPLL

parent 18ba0078
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Showing with 65 additions and 52 deletions
platform/xilinx/wr_gtp_phy/kintex7-lp/gtx_comma_detect_lp.vhd
View file @ 5c6e5607
......@@ -14,6 +14,7 @@ entity gtx_comma_detect_kintex7_lp is
rx_data_raw_i : in std_logic_vector(39 downto 0);
comma_target_pos_i : in std_logic_vector(7 downto 0);
comma_current_pos_o : out std_logic_vector(7 downto 0);
link_up_o : out std_logic;
aligned_o : out std_logic
......@@ -37,7 +38,7 @@ architecture rtl of gtx_comma_detect_kintex7_lp is
signal first_comma : std_logic_vector(7 downto 0);
signal cnt : unsigned(15 downto 0);
signal state : t_state;
signal comma_found : std_logic_vector(79 downto 0);
signal comma_found : std_logic_vector(70 downto 0);
component chipscope_ila_v6 is
port (
......@@ -120,12 +121,14 @@ begin
if rst_i = '1' then
comma_found <= (others => '0');
else
rx_data_d0 <= rx_data_raw_i;
rx_data_d1 <= rx_data_d0;
rx_data_merged <= rx_data_d1 & rx_data_d0 & rx_data_raw_i;
-- 1 8b10b bits = 4 oversampled bits
for i in 0 to 79 loop
-- 1 8b10b bit= 4 oversampled bits
for i in 0 to 70 loop
lookup := f_decimate(rx_data_merged, i, 10, 4 );
if lookup = c_K28_5_PLUS or
......@@ -140,6 +143,7 @@ begin
if unsigned(comma_found) /= 0 then
comma_pos_valid <= '1';
comma_current_pos_o <= f_onehot_encode(comma_found, comma_pos'length);
else
comma_pos_valid <= '0';
end if;
......@@ -151,8 +155,11 @@ begin
begin
if rising_edge(clk_rx_i) then
if rst_i = '1' then
state <= SYNC_LOST;
else
case state is
when SYNC_LOST =>
link_up <= '0';
......
platform/xilinx/wr_gtp_phy/kintex7-lp/gtxe2_lp.vhd
View file @ 5c6e5607
......@@ -76,7 +76,7 @@ generic
GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
SIM_CPLLREFCLK_SEL : bit_vector := "001";
PMA_RSV_IN : bit_vector := x"00018480";
PMA_RSV_IN : bit_vector := x"001E7080";
PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
);
port
......@@ -234,13 +234,13 @@ begin
------------------RX Byte and Word Alignment Attributes---------------
ALIGN_COMMA_DOUBLE => ("FALSE"),
ALIGN_COMMA_ENABLE => ("0001111111"),
ALIGN_COMMA_WORD => (2),
ALIGN_COMMA_ENABLE => ("1111111111"),
ALIGN_COMMA_WORD => (1),
ALIGN_MCOMMA_DET => ("TRUE"),
ALIGN_MCOMMA_VALUE => ("1010000011"),
ALIGN_PCOMMA_DET => ("TRUE"),
ALIGN_PCOMMA_VALUE => ("0101111100"),
SHOW_REALIGN_COMMA => ("FALSE"),
SHOW_REALIGN_COMMA => ("TRUE"),
RXSLIDE_AUTO_WAIT => (7),
RXSLIDE_MODE => ("OFF"),
RX_SIG_VALID_DLY => (10),
......@@ -252,22 +252,22 @@ begin
DEC_VALID_COMMA_ONLY => ("FALSE"),
------------------------RX Clock Correction Attributes----------------------
CBCC_DATA_SOURCE_SEL => ("DECODED"),
CBCC_DATA_SOURCE_SEL => ("ENCODED"),
CLK_COR_SEQ_2_USE => ("FALSE"),
CLK_COR_KEEP_IDLE => ("FALSE"),
CLK_COR_MAX_LAT => (10),
CLK_COR_MIN_LAT => (8),
CLK_COR_MAX_LAT => (19),
CLK_COR_MIN_LAT => (15),
CLK_COR_PRECEDENCE => ("TRUE"),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_LEN => (1),
CLK_COR_SEQ_1_ENABLE => ("1111"),
CLK_COR_SEQ_1_1 => ("0000000000"),
CLK_COR_SEQ_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2 => ("0000000000"),
CLK_COR_SEQ_1_3 => ("0000000000"),
CLK_COR_SEQ_1_4 => ("0000000000"),
CLK_CORRECT_USE => ("FALSE"),
CLK_COR_SEQ_2_ENABLE => ("1111"),
CLK_COR_SEQ_2_1 => ("0000000000"),
CLK_COR_SEQ_2_1 => ("0100000000"),
CLK_COR_SEQ_2_2 => ("0000000000"),
CLK_COR_SEQ_2_3 => ("0000000000"),
CLK_COR_SEQ_2_4 => ("0000000000"),
......@@ -372,7 +372,7 @@ begin
--For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
--For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
RXCDR_CFG => (x"03000023ff20400020"),
RXCDR_CFG => (x"03000023ff40200020"),
RXCDR_FR_RESET_ON_EIDLE => ('0'),
RXCDR_HOLD_DURING_EIDLE => ('0'),
RXCDR_PH_RESET_ON_EIDLE => ('0'),
......@@ -467,8 +467,8 @@ begin
CPLL_INIT_CFG => (x"00001E"),
CPLL_LOCK_CFG => (x"01E8"),
CPLL_REFCLK_DIV => (1),
RXOUT_DIV => (1),
TXOUT_DIV => (1),
RXOUT_DIV => (2),
TXOUT_DIV => (2),
SATA_CPLL_CFG => ("VCO_3000MHZ"),
--------------RX Initialization and Reset Attributes-------------
......@@ -512,15 +512,15 @@ begin
)
port map
(
--------------------------------- CPLL Ports -------------------------------
CPLLFBCLKLOST => CPLLFBCLKLOST_OUT,
CPLLLOCK => CPLLLOCK_OUT,
CPLLLOCKDETCLK => CPLLLOCKDETCLK_IN,
--------------------------------- CPLL Ports -------------------------------
CPLLFBCLKLOST => open,
CPLLLOCK => open,
CPLLLOCKDETCLK => tied_to_ground_i,
CPLLLOCKEN => tied_to_vcc_i,
CPLLPD => tied_to_ground_i,
CPLLREFCLKLOST => CPLLREFCLKLOST_OUT,
CPLLPD => tied_to_vcc_i,
CPLLREFCLKLOST => open,
CPLLREFCLKSEL => "001",
CPLLRESET => CPLLRESET_IN,
CPLLRESET => tied_to_ground_i,
GTRSVD => "0000000000000000",
PCSRSVDIN => "0000000000000000",
PCSRSVDIN2 => "00000",
......@@ -534,7 +534,7 @@ begin
GTGREFCLK => tied_to_ground_i,
GTNORTHREFCLK0 => tied_to_ground_i,
GTNORTHREFCLK1 => tied_to_ground_i,
GTREFCLK0 => GTREFCLK0_IN,
GTREFCLK0 => tied_to_ground_i,
GTREFCLK1 => tied_to_ground_i,
GTSOUTHREFCLK0 => tied_to_ground_i,
GTSOUTHREFCLK1 => tied_to_ground_i,
......@@ -548,16 +548,16 @@ begin
DRPWE => DRPWE_IN,
------------------------------- Clocking Ports -----------------------------
GTREFCLKMONITOR => open,
QPLLCLK => QPLLCLK_IN,
QPLLREFCLK => QPLLREFCLK_IN,
RXSYSCLKSEL => "00",
TXSYSCLKSEL => "00",
QPLLCLK => qpllclk_in,
QPLLREFCLK => qpllrefclk_in,
RXSYSCLKSEL => "11",
TXSYSCLKSEL => "11",
--------------------------- Digital Monitor Ports --------------------------
DMONITOROUT => open,
----------------- FPGA TX Interface Datapath Configuration ----------------
TX8B10BEN => '0',
------------------------------- Loopback Ports -----------------------------
LOOPBACK => LOOPBACK_IN,
LOOPBACK => tied_to_ground_vec_i(2 downto 0), --LOOPBACK_IN,
----------------------------- PCI Express Ports ----------------------------
PHYSTATUS => open,
RXRATE => tied_to_ground_vec_i(2 downto 0),
......@@ -599,7 +599,7 @@ begin
------------------- Receive Ports - Pattern Checker ports ------------------
RXPRBSCNTRESET => tied_to_ground_i,
-------------------- Receive Ports - RX Equalizer Ports -------------------
RXDFEXYDEN => tied_to_ground_i,
RXDFEXYDEN => tied_to_vcc_i,
RXDFEXYDHOLD => tied_to_ground_i,
RXDFEXYDOVRDEN => tied_to_ground_i,
--------------------------- Receive Ports - RX AFE -------------------------
......@@ -643,7 +643,7 @@ begin
RXDFEAGCOVRDEN => tied_to_ground_i,
RXDFECM1EN => tied_to_ground_i,
RXDFELFHOLD => tied_to_ground_i,
RXDFELFOVRDEN => tied_to_ground_i,
RXDFELFOVRDEN => tied_to_vcc_i,
RXDFELPMRESET => tied_to_ground_i,
RXDFETAP2HOLD => tied_to_ground_i,
RXDFETAP2OVRDEN => tied_to_ground_i,
......@@ -687,7 +687,7 @@ begin
RXPCSRESET => tied_to_ground_i,
RXPMARESET => RXPMARESET_IN,
------------------ Receive Ports - RX Margin Analysis ports ----------------
RXLPMEN => tied_to_vcc_i,
RXLPMEN => tied_to_ground_i,
------------------- Receive Ports - RX OOB Signaling ports -----------------
RXCOMSASDET => open,
RXCOMWAKEDET => open,
......@@ -776,7 +776,7 @@ begin
TXOUTCLK => TXOUTCLK_OUT,
TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT,
TXOUTCLKPCS => TXOUTCLKPCS_OUT,
TXOUTCLKSEL => "010",
TXOUTCLKSEL => "011",
TXRATEDONE => open,
--------------------- Transmit Ports - TX Gearbox Ports --------------------
TXCHARISK(7 downto 2) => tied_to_ground_vec_i(5 downto 0),
......@@ -808,7 +808,7 @@ begin
TXQPISENP => open
);
end RTL;
......
platform/xilinx/wr_gtp_phy/kintex7-lp/wr_gtx_phy_kintex7_lp.vhd
View file @ 5c6e5607
......@@ -6,7 +6,7 @@
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
-- Last update: 2019-06-05
-- Last update: 2019-06-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -61,8 +61,12 @@ entity wr_gtx_phy_kintex7_lp is
);
port (
-- Dedicated reference 125 MHz clock for the GTX transceiver
clk_gtx_i : in std_logic;
qpll_clk_i : in std_logic;
qpll_ref_clk_i : in std_logic;
qpll_locked_i : in std_logic;
-- DMTD clock for phase measurements (done in the PHY module as we need to
-- multiplex between several GTX clock outputs)
......@@ -176,9 +180,8 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
signal tx_rst_done, rx_rst_done : std_logic;
signal txpll_lockdet, rxpll_lockdet : std_logic;
signal pll_lockdet : std_logic;
signal cpll_lockdet : std_logic;
signal gtreset : std_logic;
-- signal pll_lockdet : std_logic;
-- signal cpll_lockdet : std_logic;
signal everything_ready : std_logic;
signal rst_done : std_logic;
......@@ -239,6 +242,7 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
end function;
signal comma_target_pos : std_logic_vector(7 downto 0);
signal comma_current_pos : std_logic_vector(7 downto 0);
begin -- rtl
......@@ -342,7 +346,7 @@ begin -- rtl
gtx_rst <= rst_synced or std_logic(not reset_counter(reset_counter'left));
debug_o(0) <= '1'; -- was tx_reset_done
debug_o(0) <= qpll_locked_i; -- was tx_reset_done
tx_enc_err_o <= '0';
......@@ -351,8 +355,8 @@ begin -- rtl
I => tx_out_clk_bufin,
O => tx_out_clk);
tx_clk_o <= tx_out_clk;
tx_locked_o <= cpll_lockdet;
tx_clk_o <= tx_out_clk;
tx_locked_o <= qpll_locked_i;
U_BUF_RxRecClk : BUFG
port map (
......@@ -380,12 +384,12 @@ begin -- rtl
(
--------------------------------- CPLL Ports -------------------------------
CPLLFBCLKLOST_OUT => open,
CPLLLOCK_OUT => cpll_lockdet,
CPLLLOCK_OUT => open,
CPLLLOCKDETCLK_IN => '0',
CPLLREFCLKLOST_OUT => open,
CPLLRESET_IN => gtx_tx_reset_a,
CPLLRESET_IN => '0',
-------------------------- Channel - Clocking Ports ------------------------
GTREFCLK0_IN => clk_gtx_i,
GTREFCLK0_IN => '0',
---------------------------- Channel - DRP Ports --------------------------
DRPADDR_IN => (Others => '0'),
DRPCLK_IN => '0',
......@@ -395,8 +399,8 @@ begin -- rtl
DRPRDY_OUT => open,
DRPWE_IN => '0',
------------------------------- Clocking Ports -----------------------------
QPLLCLK_IN => '0',
QPLLREFCLK_IN => '0',
QPLLCLK_IN => qpll_clk_i,
QPLLREFCLK_IN => qpll_ref_clk_i,
------------------------------- Loopback Ports -----------------------------
LOOPBACK_IN => gtx_loopback,
--------------------- RX Initialization and Reset Ports --------------------
......@@ -428,7 +432,7 @@ begin -- rtl
RXRESETDONE_OUT => rx_rst_done,
--------------------- TX Initialization and Reset Ports --------------------
GTTXRESET_IN => gtx_tx_reset_a,
TXUSERRDY_IN => cpll_lockdet,
TXUSERRDY_IN => qpll_locked_i,
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXUSRCLK_IN => tx_out_clk,
TXUSRCLK2_IN => tx_out_clk,
......@@ -450,13 +454,12 @@ begin -- rtl
txpll_lockdet <= cpll_lockdet;
txpll_lockdet <= qpll_locked_i;
rxpll_lockdet <= rx_cdr_lock_filtered;
gtreset <= not cpll_lockdet;
rst_done <= rx_rst_done and tx_rst_done;
rst_done_n <= not rst_done;
pll_lockdet <= txpll_lockdet and rxpll_lockdet;
everything_ready <= rst_done and pll_lockdet;
-- pll_lockdet <= txpll_lockdet and rxpll_lockdet;
everything_ready <= rst_done and txpll_lockdet and rxpll_lockdet; --pll_lockdet;
rdy_o <= everything_ready;
......@@ -508,7 +511,8 @@ begin -- rtl
clk_rx_i => rx_rec_clk,
rst_i => gtx_rst,
rx_data_raw_i => rx_data_raw,
comma_target_pos_i =>
comma_target_pos_i => comma_target_pos,
comma_current_pos_o => comma_current_pos,
link_up_o => link_up,
aligned_o => link_aligned);
......@@ -541,6 +545,8 @@ begin -- rtl
debug_o(1) <= link_up;
debug_o(2) <= link_aligned;
debug_o(14 downto 7) <= comma_current_pos;
p_gen_rx_outputs : process(rx_rec_clk, gtx_rst)
begin
if(gtx_rst = '1') then
......
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