dmtd_sampler: initialize clock divider flip-flop, added to Manifest

618d4f6d · Tomasz Wlostowski · Grzegorz Daniluk · 41b25aba · 618d4f6d · 618d4f6d
Commit 618d4f6d authored Jun 19, 2019 by Tomasz Wlostowski Committed by Grzegorz Daniluk Sep 15, 2020
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Manifest.py modules/timing/Manifest.py +1 -0

dmtd_sampler.vhd modules/timing/dmtd_sampler.vhd +2 -2

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--- a/modules/timing/Manifest.py
+++ b/modules/timing/Manifest.py
 files = ["dmtd_phase_meas.vhd",
         "dmtd_with_deglitcher.vhd",
+	 "dmtd_sampler.vhd",
         "multi_dmtd_with_deglitcher.vhd",
         "hpll_period_detect.vhd",
         "pulse_gen.vhd",

--- a/modules/timing/dmtd_sampler.vhd
+++ b/modules/timing/dmtd_sampler.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-02-25
-- Last update: 2017-06-23
+-- Last update: 2019-06-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL '93
 -------------------------------------------------------------------------------
@@ -66,7 +66,7 @@ end dmtd_sampler;
 architecture rtl of dmtd_sampler is


-  signal clk_in                                           : std_logic;
+  signal clk_in                                           : std_logic := '0';
  signal clk_i_d0, clk_i_d1, clk_i_d2, clk_i_d3, clk_i_dx : std_logic;

  attribute keep             : string;