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White Rabbit core collection
Commit 4e9d0763 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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platform: phase-stable GTXE2 wrapper (Kintex7), initial version

parent 678491f4
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Showing with 498 additions and 188 deletions
platform/xilinx/wr_gtp_phy/Manifest.py
View file @ 4e9d0763
......@@ -30,8 +30,12 @@ elif (syn_device[0:4].upper()=="XC7K" or # Family 7 GTX (Kintex7 and Virtex7 585
syn_device[0:7].upper()=="XC7V585" or
syn_device[0:8].upper()=="XC7V2000" or
syn_device[0:8].upper()=="XC7VX485"):
files.extend(["family7-gtx/wr_gtx_phy_family7.vhd",
"family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"]);
files.extend([
# "family7-gtx/wr_gtx_phy_family7.vhd",
# "family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd",
"kintex7-lp/gtx_comma_detect_lp.vhd",
"kintex7-lp/wr_gtx_phy_kintex7_lp.vhd",
"kintex7-lp/gtxe2_lp.vhd"]);
elif (syn_device[0:4].upper()=="XC7V"): # Family 7 GTH (other Virtex7 devices)
files.extend(["family7-gth/wr_gth_phy_family7.vhd",
"whiterabbit_gthe2_channel_wrapper_gt.vhd",
......
platform/xilinx/wr_gtp_phy/kintex7-lp/gtx_comma_detect_lp.vhd 0 → 100644
View file @ 4e9d0763
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtx_comma_detect_lp is
generic (
g_ID : integer
);
port (
clk_rx_i : in std_logic;
rst_i : in std_logic;
rx_data_raw_i : in std_logic_vector(19 downto 0);
link_up_o : out std_logic;
aligned_o : out std_logic;
rx_data_i : in std_logic_vector(15 downto 0);
rx_k_i : in std_logic_vector(1 downto 0);
rx_error_i : in std_logic
);
end gtx_comma_detect_lp;
architecture rtl of gtx_comma_detect_lp is
type t_state is (SYNC_LOST, SYNC_CHECK, SYNC_ACQUIRED);
constant c_IDLE_LENGTH_UP : integer := 500;
constant c_IDLE_LENGTH_LOSS : integer := 1000;
constant c_COMMA_SHIFT_WE_WANT : std_logic_vector(6 downto 0) := "0110000";
-- fixme
signal rx_data_d0 : std_logic_vector(19 downto 0);
signal rx_data_merged : std_logic_vector(49 downto 0);
signal first_comma : std_logic_vector(4 downto 0);
signal cnt : unsigned(15 downto 0);
signal state : t_state;
signal comma_found : std_logic_vector(19 downto 0);
component chipscope_ila_v6 is
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(63 downto 0));
end component chipscope_ila_v6;
component chipscope_icon_v6 is
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component chipscope_icon_v6;
signal CONTROL : std_logic_vector(35 downto 0);
signal TRIG0 : std_logic_vector(63 downto 0);
function f_onehot_encode (x : std_logic_vector; output_bits : integer)return std_logic_vector is
variable rv : std_logic_vector(output_bits-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
rv := std_logic_vector(to_unsigned(i, output_bits));
return rv;
end if;
end loop;
return std_logic_vector(to_unsigned(0, output_bits));
end f_onehot_encode;
constant c_K28_5_PLUS : std_logic_vector(9 downto 0) := "1010000011";
signal comma_pos : std_logic_vector(4 downto 0);
signal prev_comma_pos : std_logic_vector(4 downto 0);
signal prev_comma_pos_valid : std_logic;
signal comma_pos_valid : std_logic;
signal link_up : std_logic;
signal link_aligned : std_logic;
begin
-- gen1 : if g_id = 0 generate
-- chipscope_icon_1 : chipscope_icon_v6
-- port map (
-- CONTROL0 => CONTROL);
-- chipscope_ila_1 : chipscope_ila_v6
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_rx_i,
-- TRIG0 => TRIG0);
-- trig0 (19 downto 0) <= rx_data_raw_i;
-- trig0 (39 downto 20) <= comma_found;
-- trig0 (40) <= comma_pos_valid;
-- trig0 (41) <= link_up;
-- trig0 (42) <= link_aligned;
-- trig0 (43+15 downto 43) <= std_logic_vector(cnt);
-- end generate gen1;
process(clk_rx_i)
begin
if rising_edge(clk_rx_i) then
if rst_i = '1' then
comma_found <= (others => '0');
else
rx_data_d0 <= rx_data_raw_i;
rx_data_merged(39 downto 0) <= rx_data_d0 & rx_data_raw_i;
for i in 0 to 19 loop
if rx_data_merged(i + 9 downto i) = c_K28_5_PLUS or
rx_data_merged(i + 9 downto i) = (not c_K28_5_PLUS) then
comma_found(i) <= '1';
else
comma_found(i) <= '0';
end if;
end loop;
comma_pos <= f_onehot_encode(comma_found, comma_pos'length);
if unsigned(comma_found) /= 0 then
comma_pos_valid <= '1';
else
comma_pos_valid <= '0';
end if;
end if;
end if;
end process;
process(clk_rx_i)
begin
if rising_edge(clk_rx_i) then
if rst_i = '1' then
state <= SYNC_LOST;
else
case state is
when SYNC_LOST =>
link_up <= '0';
link_aligned <= '0';
if comma_pos_valid = '1' then
first_comma <= comma_pos;
state <= SYNC_CHECK;
cnt <= to_unsigned(4, cnt'length);
end if;
when SYNC_CHECK =>
if comma_pos = first_comma and comma_pos_valid = '1' then
cnt <= cnt + 4;
elsif cnt > 0 then
cnt <= cnt - 1;
if cnt = 1 then
state <= SYNC_LOST;
end if;
end if;
if cnt >= c_IDLE_LENGTH_UP then
state <= SYNC_ACQUIRED;
cnt <= (others => '0');
end if;
when SYNC_ACQUIRED =>
link_up <= '1';
if(comma_pos_valid = '1' and comma_pos = first_comma) then
if(unsigned(comma_pos) = 0) then
link_aligned <= '1';
end if;
cnt <= (others => '0');
else
cnt <= cnt + 1;
if cnt = c_IDLE_LENGTH_LOSS then
state <= SYNC_LOST;
end if;
end if;
end case;
end if;
end if;
end process;
aligned_o <= link_aligned;
link_up_o <= link_up;
end rtl;
platform/xilinx/wr_gtxe2_channel_wrapper_gt.vhd → platform/xilinx/wr_gtp_phy/kintex7-lp/gtxe2_lp.vhd
View file @ 4e9d0763
......@@ -113,16 +113,12 @@ port
RXUSRCLK2_IN : in std_logic;
------------------ Receive Ports - FPGA RX interface Ports -----------------
RXDATA_OUT : out std_logic_vector(15 downto 0);
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXDISPERR_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
RXCHARISK_OUT : out std_logic_vector(1 downto 0);
RXDISPERR_OUT : out std_logic_vector(1 downto 0);
--------------------------- Receive Ports - RX AFE -------------------------
GTXRXP_IN : in std_logic;
------------------------ Receive Ports - RX AFE Ports ----------------------
GTXRXN_IN : in std_logic;
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED_OUT : out std_logic;
RXCOMMADET_OUT : out std_logic;
--------------------- Receive Ports - RX Equilizer Ports -------------------
RXLPMHFHOLD_IN : in std_logic;
RXLPMLFHOLD_IN : in std_logic;
......@@ -131,10 +127,6 @@ port
------------- Receive Ports - RX Initialization and Reset Ports ------------
GTRXRESET_IN : in std_logic;
RXPMARESET_IN : in std_logic;
---------------------- Receive Ports - RX gearbox ports --------------------
RXSLIDE_IN : in std_logic;
------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
RXCHARISK_OUT : out std_logic_vector(1 downto 0);
-------------- Receive Ports -RX Initialization and Reset Ports ------------
RXRESETDONE_OUT : out std_logic;
--------------------- TX Initialization and Reset Ports --------------------
......@@ -178,8 +170,8 @@ architecture RTL of whiterabbit_gtxe2_channel_wrapper_GT is
-- RX Datapath signals
signal rxdata_i : std_logic_vector(63 downto 0);
signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
signal rxcharisk_float_i : std_logic_vector(5 downto 0);
signal rxdisperr_float_i : std_logic_vector(5 downto 0);
signal rxcharisk_i : std_logic_vector(7 downto 0);
signal rxdisperr_i : std_logic_vector(7 downto 0);
signal rxnotintable_float_i : std_logic_vector(5 downto 0);
signal rxrundisp_float_i : std_logic_vector(5 downto 0);
......@@ -204,6 +196,9 @@ begin
------------------- GT Datapath byte mapping -----------------
RXDATA_OUT <= rxdata_i(15 downto 0);
RXCHARISK_OUT <= rxcharisk_i(1 downto 0);
RXDISPERR_OUT <= rxdisperr_i(1 downto 0);
txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
......@@ -234,7 +229,7 @@ begin
ALIGN_PCOMMA_VALUE => ("0101111100"),
SHOW_REALIGN_COMMA => ("FALSE"),
RXSLIDE_AUTO_WAIT => (7),
RXSLIDE_MODE => ("PCS"),
RXSLIDE_MODE => ("OFF"),
RX_SIG_VALID_DLY => (10),
------------------RX 8B/10B Decoder Attributes---------------
......@@ -351,8 +346,7 @@ begin
--For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200002
--For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h03000023ff10200020
RXCDR_CFG => (x"03000023ff10100020"),
RXCDR_CFG => (x"03000023ff40100020"),
RXCDR_FR_RESET_ON_EIDLE => ('0'),
RXCDR_HOLD_DURING_EIDLE => ('0'),
RXCDR_PH_RESET_ON_EIDLE => ('0'),
......@@ -397,7 +391,7 @@ begin
TRANS_TIME_RATE => (x"0E"),
--------------TX Buffer Attributes----------------
TXBUF_EN => ("TRUE"),
TXBUF_EN => ("FALSE"),
TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
TXDLY_CFG => (x"001F"),
TXDLY_LCFG => (x"030"),
......@@ -565,12 +559,15 @@ begin
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => open,
---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
RX8B10BEN => tied_to_vcc_i,
RX8B10BEN => tied_to_ground_i,
------------------ Receive Ports - FPGA RX Interface Ports -----------------
RXUSRCLK => RXUSRCLK_IN,
RXUSRCLK2 => RXUSRCLK2_IN,
------------------ Receive Ports - FPGA RX interface Ports -----------------
RXDATA => rxdata_i,
RXCHARISK => rxcharisk_i,
RXDISPERR => rxdisperr_i,
------------------- Receive Ports - Pattern Checker Ports ------------------
RXPRBSERR => open,
RXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
......@@ -580,11 +577,6 @@ begin
RXDFEXYDEN => tied_to_ground_i,
RXDFEXYDHOLD => tied_to_ground_i,
RXDFEXYDOVRDEN => tied_to_ground_i,
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXDISPERR(7 downto 2) => rxdisperr_float_i,
RXDISPERR(1 downto 0) => RXDISPERR_OUT,
RXNOTINTABLE(7 downto 2) => rxnotintable_float_i,
RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT,
--------------------------- Receive Ports - RX AFE -------------------------
GTXRXP => GTXRXP_IN,
------------------------ Receive Ports - RX AFE Ports ----------------------
......@@ -608,9 +600,6 @@ begin
RXPHSLIPMONITOR => open,
RXSTATUS => open,
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED => RXBYTEISALIGNED_OUT,
RXBYTEREALIGN => open,
RXCOMMADET => RXCOMMADET_OUT,
RXCOMMADETEN => tied_to_vcc_i,
RXMCOMMAALIGNEN => tied_to_ground_i,
RXPCOMMAALIGNEN => tied_to_ground_i,
......@@ -685,11 +674,9 @@ begin
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY => tied_to_ground_i,
---------------------- Receive Ports - RX gearbox ports --------------------
RXSLIDE => RXSLIDE_IN,
RXSLIDE => '0',
------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
RXCHARISCOMMA => open,
RXCHARISK(7 downto 2) => rxcharisk_float_i,
RXCHARISK(1 downto 0) => RXCHARISK_OUT,
------------------ Receive Ports - Rx Channel Bonding Ports ----------------
RXCHBONDI => "00000",
-------------- Receive Ports -RX Initialization and Reset Ports ------------
......
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