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White Rabbit core collection
Commit fcc50b04 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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wr_core: expose SoftPLL's g_use_sampled_ref_clocks generic & associated interface

parent 5363943e
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Showing with 35 additions and 3 deletions
modules/wrc_core/wr_core.vhd
View file @ fcc50b04
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2019-02-01
-- Last update: 2019-03-29
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -92,6 +92,7 @@ entity wr_core is
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_enable_debugger : boolean := false;
g_softpll_use_sampled_ref_clocks : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
......@@ -161,6 +162,11 @@ entity wr_core is
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_rx_rbclk_sampled_i : in std_logic;
phy_debug_o : out std_logic_vector(15 downto 0);
phy_debug_i : in std_logic_vector(15 downto 0);
-- PHY I/F record-based
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
......@@ -655,6 +661,7 @@ begin
g_num_outputs => 1 + g_aux_clks,
g_num_exts => f_num_ext_clks,
g_ref_clock_rate => f_refclk_rate(g_pcs_16bit),
g_use_sampled_ref_clocks => g_softpll_use_sampled_ref_clocks,
g_ext_clock_rate => 10000000)
port map(
clk_sys_i => clk_sys_i,
......@@ -665,6 +672,7 @@ begin
-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
clk_ref_i(0) => phy_rx_clk,
clk_ref_sampled_i(0) => phy_rx_rbclk_sampled_i,
-- Feedback clocks (i.e. the outputs of the main or aux oscillator)
clk_fb_i => clk_fb,
-- DMTD Offset clock
......@@ -777,6 +785,8 @@ begin
phy_rx_k_i => phy_rx_k_i,
phy_rx_enc_err_i => phy_rx_enc_err_i,
phy_rx_bitslide_i => phy_rx_bitslide_i,
phy_debug_o => phy_debug_o,
phy_debug_i => phy_debug_i,
phy8_o => phy8_o,
phy8_i => phy8_i,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ fcc50b04
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11
-- Last update: 2019-02-01
-- Last update: 2019-03-29
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -320,6 +320,7 @@ package wrcore_pkg is
g_divide_input_by_2 : boolean;
g_ref_clock_rate : integer;
g_ext_clock_rate : integer;
g_use_sampled_ref_clocks : boolean := false;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
......@@ -330,6 +331,7 @@ package wrcore_pkg is
rst_dmtd_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_ref_sampled_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) := (others => '0');
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
......@@ -377,6 +379,7 @@ package wrcore_pkg is
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_enable_debugger : boolean := false;
g_softpll_use_sampled_ref_clocks : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
......@@ -422,6 +425,10 @@ package wrcore_pkg is
phy_sfp_tx_fault_i : in std_logic := '0';
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_rx_rbclk_sampled_i : in std_logic := '0';
phy_debug_o : out std_logic_vector(15 downto 0);
phy_debug_i : in std_logic_vector(15 downto 0) := x"0000";
-----------------------------------------
-- PHY I/f - record-based
-- selection done with g_records_for_phy
......@@ -521,6 +528,7 @@ package wrcore_pkg is
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_enable_debugger : boolean := false;
g_softpll_use_sampled_ref_clocks : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
......@@ -591,6 +599,11 @@ package wrcore_pkg is
phy_sfp_tx_fault_i : in std_logic := '0';
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_rx_rbclk_sampled_i : in std_logic := '0';
phy_debug_o : out std_logic_vector(15 downto 0);
phy_debug_i : in std_logic_vector(15 downto 0) := x"0000";
-----------------------------------------
-- PHY I/f - record-based
-- selection done with g_records_for_phy
......
modules/wrc_core/xwr_core.vhd
View file @ fcc50b04
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2019-02-01
-- Last update: 2019-03-29
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -91,6 +91,7 @@ entity xwr_core is
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_enable_debugger : boolean := false;
g_softpll_use_sampled_ref_clocks : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
......@@ -149,10 +150,14 @@ entity xwr_core is
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_rbclk_sampled_i : in std_logic;
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_debug_i : in std_logic_vector(15 downto 0);
phy_rst_o : out std_logic;
phy_rdy_i : in std_logic := '1';
phy_loopen_o : out std_logic;
......@@ -293,6 +298,7 @@ begin
g_address_granularity => g_address_granularity,
g_aux_sdb => g_aux_sdb,
g_softpll_enable_debugger => g_softpll_enable_debugger,
g_softpll_use_sampled_ref_clocks => g_softpll_use_sampled_ref_clocks,
g_vuart_fifo_size => g_vuart_fifo_size,
g_pcs_16bit => g_pcs_16bit,
g_records_for_phy => g_records_for_phy,
......@@ -326,6 +332,7 @@ begin
phy_tx_enc_err_i => phy_tx_enc_err_i,
phy_rx_data_i => phy_rx_data_i,
phy_rx_rbclk_i => phy_rx_rbclk_i,
phy_rx_rbclk_sampled_i => phy_rx_rbclk_sampled_i,
phy_rx_k_i => phy_rx_k_i,
phy_rx_enc_err_i => phy_rx_enc_err_i,
phy_rx_bitslide_i => phy_rx_bitslide_i,
......@@ -333,6 +340,8 @@ begin
phy_rdy_i => phy_rdy_i,
phy_loopen_o => phy_loopen_o,
phy_loopen_vec_o => phy_loopen_vec_o,
phy_debug_o => phy_debug_o,
phy_debug_i => phy_debug_i,
phy_tx_prbs_sel_o => phy_tx_prbs_sel_o,
phy_sfp_tx_fault_i => phy_sfp_tx_fault_i,
phy_sfp_los_i => phy_sfp_los_i,
......
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