wr_softpll_ng: added support for external DDMTD sampler

5363943e · Tomasz Wlostowski · Grzegorz Daniluk · 4e9d0763 · 5363943e
Commit 5363943e authored Jul 07, 2017 by Tomasz Wlostowski Committed by Grzegorz Daniluk Sep 15, 2020
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xwr_softpll_ng.vhd modules/wr_softpll_ng/xwr_softpll_ng.vhd +1 -1

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--- a/modules/wr_softpll_ng/xwr_softpll_ng.vhd
+++ b/modules/wr_softpll_ng/xwr_softpll_ng.vhd
@@ -109,7 +109,7 @@ entity xwr_softpll_ng is
    clk_ext_mul_locked_i : in std_logic := '1';
    clk_ext_stopped_i    : in std_logic := '0';
    clk_ext_rst_o        : out std_logic;
-	 
+
 -- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0)
 -- to match the edges immediately following the rising edge in sync_p_i.
    pps_csync_p1_i : in std_logic;