Missing reset values

See merge request !11

Add some missing reset values, so the signals propagated to the WB are not 'X' when the simulation starts.

Cf:
https://support.xilinx.com/s/question/0D54U00005cVSUySAO/how-does-vivado-deal-with-vhdl-slice-assignment-with-opposite-directions?language=en_US&t=1664456754676

If g_ASYNC_DTACK is set to true (the default is false), /DTACK is
asynchronously driven by /DS.  In that case, the release of /DTACK
must be read from the async driver to handle fast changes.

Fix a typo in a comment

Fix issue#18

Dab64x shared vme

See merge request !4

Expose card_sel signal at the top of vme_bus module (for shared VME on Dab64x board). Leave it open in the upper blocks if unused.

Fix verilog wrapper

See merge request !3

VME Core 64x wrapper for Verilog instantiation.

See merge request !2

Change the generic assignment per index/field in a record type, because it is…

See merge request !1

Change the generic assignment per index/field in a record type, because it is not compatible with some synthesizers (Synplify for instance).

Use transfer rate to select number of cycles for setup and hold.
Prefetch earlier.

In the previous code, a function that is selected but not supported for the AM was masking any
following function.

And wait until WB transfers are done before accepting a new VME
transaction.