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VME64x core
Commit e1f6b40e authored by Tristan Gingold's avatar Tristan Gingold
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vme_bus: do not stop WB transfers. 

And wait until WB transfers are done before accepting a new VME
transaction.
parent 91e43d01
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Showing with 22 additions and 27 deletions
hdl/rtl/vme_bus.vhd
View file @ e1f6b40e
......@@ -375,16 +375,19 @@ begin
s_transferType <= TFR_ERROR;
-- Address will be put to addr_reg.
load_addr_reg_phase1 <= '1';
if vme_iack_n_i = '1' then
if vme_iack_n_i = '0' then
-- IACK cycle.
s_mainFSMstate <= IRQ_CHECK;
elsif s_WBFSMstate /= IDLE then
-- Not yet read.
null;
else
-- Address will be put to addr_reg.
load_addr_reg_phase1 <= '1';
-- ANSI/VITA 1-1994 Rule 2.11
-- Slaves MUST NOT respond to DTB cycles when IACK* is low.
s_mainFSMstate <= REFORMAT_ADDRESS;
else
-- IACK cycle.
s_mainFSMstate <= IRQ_CHECK;
end if;
when REFORMAT_ADDRESS =>
......@@ -876,7 +879,7 @@ begin
p_WB_FSM : process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_n_i = '0' or vme_as_n_i = '1' then
if rst_n_i = '0' then
-- FSM reset after power up,
-- software reset, manually reset,
-- on rising edge of AS.
......@@ -895,9 +898,9 @@ begin
else
case s_WBFSMstate is
when IDLE =>
-- Can only be here if vme_as_n_i has fallen to 0, which starts a
-- cycle.
assert vme_as_n_i = '0';
wb_cyc_o <= '0';
wb_stb_o <= '0';
if load_addr_reg_phase1 = '1' then
-- VME address phase 1.
......@@ -1013,24 +1016,20 @@ begin
end if;
when MEMORY_REQ =>
-- To request the memory CR/CSR or WB memory it is sufficient to
-- generate a pulse on s_conf_req signal
-- Assert STB if stall was asserted.
case g_WB_MODE is
when CLASSIC =>
-- Maintain STB.
wb_stb_o <= s_card_sel;
wb_stb_o <= '1';
when PIPELINED =>
-- Maintain STB if stall was set in the previous cycle.
wb_stb_o <= s_card_sel and s_stall and wb_stall_i;
wb_stb_o <= s_stall and wb_stall_i;
end case;
s_stall <= s_stall and wb_stall_i;
if s_conf_sel = '1'
or (s_card_sel = '1' and (wb_ack_i = '1' or wb_err_i = '1'))
then
if wb_ack_i = '1' or wb_err_i = '1' then
-- WB ack
wb_stb_o <= '0';
......@@ -1051,7 +1050,7 @@ begin
end if;
end if;
if (s_card_sel and wb_err_i) = '1' then
if wb_err_i = '1' then
-- Error
s_err <= '1';
s_WBFSMstate <= IDLE;
......@@ -1077,16 +1076,12 @@ begin
-- Mux (CS-CSR or WB)
data_reg(63 downto 32) <= data_reg(31 downto 0);
data_reg(31 downto 0) <= (others => '0');
if s_card_sel = '1' then
if g_VME32 and addr_reg(0) = '1' and addr_reg(1) = '0'
then
-- Word/byte access with A1 = 0 on a 32bit bus.
data_reg(15 downto 0) <= wb_dat_i(31 downto 16);
else
data_reg(31 downto 0) <= wb_dat_i;
end if;
if g_VME32 and addr_reg(0) = '1' and addr_reg(1) = '0'
then
-- Word/byte access with A1 = 0 on a 32bit bus.
data_reg(15 downto 0) <= wb_dat_i(31 downto 16);
else
data_reg(7 downto 0) <= cr_csr_data_i;
data_reg(31 downto 0) <= wb_dat_i;
end if;
if s_wb_dataPhase = '1' and g_VME32 then
......
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