Add verilog wrapper in Manifest.py

ca57317a · Tristan Gingold · 2d7930f8 · ca57317a
Commit ca57317a authored Jun 22, 2022 by Tristan Gingold
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Manifest.py hdl/rtl/Manifest.py +2 -1

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--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
@@ -5,4 +5,5 @@ files = [ "vme64x_core.vhd",
          "vme_funct_match.vhd",
          "vme_irq_controller.vhd",
          "vme_user_csr.vhd",
-          "xvme64x_core.vhd"]
+          "xvme64x_core.vhd",
+          "vme64x_core_verilog.vhd"]