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Stale branches

  • sowarzan-rf
    02a397d1 · hdl/rtl/xvme64x_core.vhd | hdl/rtl/vme64x_core_verilog.vhd add default return for functions · Dec 20, 2022
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  • master default
    a0ca042e · xvme64x_core.vhd: workaround vivado 2020 bug. · Sep 30, 2022
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  • tom-rf
    42f6c768 · HDL: fixes in the verilog wrapper of the core · Sep 13, 2022
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  • tom-svec7
    833193f0 · rtl: some renaming in bridged mode: master -> SYS(FPGA), slave->APP(FPGA) · Sep 06, 2021
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  • cvora-jul15
    6d2b770e · hdl: improved static generation of ADER regsisters (non-64x mode with base address switch) · Jul 15, 2020
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